Patents by Inventor Zicheng XU
Zicheng XU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11716091Abstract: A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.Type: GrantFiled: January 7, 2020Date of Patent: August 1, 2023Assignees: No. 24 Research Institute Of China Electronics Technology Group Corporation, Chongqing GigaChip Technology Co., Ltd.Inventors: Tao Liu, Jian'an Wang, Yuxin Wang, Shengdong Hu, Zhou Yu, Minming Deng, Daiguo Xu, Lu Liu, Dongbing Fu, Jun Luo, Xu Wang, Yan Wang, Zicheng Xu
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Patent number: 11664794Abstract: The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.Type: GrantFiled: January 7, 2020Date of Patent: May 30, 2023Assignees: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Ting Li, Zhengbo Huang, Yong Zhang, Yabo Ni, Jian'an Wang, Guangbing Chen, Dongbing Fu, Zicheng Xu
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Publication number: 20220304538Abstract: A method for cleaning the mop of a cleaning robot includes: obtaining mop usage information after the cleaning robot carries the mop to clean the floor, and selecting a target mop cleaning mode to clean the mop according to the mop usage information.Type: ApplicationFiled: December 13, 2021Publication date: September 29, 2022Inventors: Yongting Cai, Zicheng Xu, Zhenhua Wen, Ziyun Cheng
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Patent number: 11394389Abstract: The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.Type: GrantFiled: December 13, 2018Date of Patent: July 19, 2022Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Ting Li, Gangyi Hu, Ruzhang Li, Yong Zhang, Zhengbo Huang, Yabo Ni, Xingfa Huang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Jun Yuan, Zicheng Xu
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Publication number: 20220224350Abstract: A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.Type: ApplicationFiled: January 7, 2020Publication date: July 14, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Tao LIU, Jian'an WANG, Yuxin WANG, Shengdong HU, Zhou YU, Minming DENG, Daiguo XU, Lu LIU, Dongbing FU, Jun LUO, Xu WANG, Yan WANG, Zicheng XU
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Publication number: 20220224320Abstract: The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.Type: ApplicationFiled: January 7, 2020Publication date: July 14, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Ting LI, Zhengbo HUANG, Yong ZHANG, Yabo NI, Jian'an WANG, Guangbing CHEN, Dongbing FU, Zicheng XU
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Publication number: 20210281269Abstract: The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.Type: ApplicationFiled: December 13, 2018Publication date: September 9, 2021Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Ting LI, Gangyi HU, Ruzhang LI, Yong ZHANG, Zhengbo HUANG, Yabo NI, Xingfa HUANG, Jian'an WANG, Guangbing CHEN, Dongbing FU, Jun YUAN, Zicheng XU