Patents by Inventor Zied Marrakchi
Zied Marrakchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10120019Abstract: The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.Type: GrantFiled: July 8, 2014Date of Patent: November 6, 2018Assignee: Mentor Graphics CorporationInventors: Matthieu Tuna, Zied Marrakchi, Christophe Alexandre
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Patent number: 9817934Abstract: The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises steps of: —partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising: —inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; —and the number of crossings of programmable chips of a critical combinatorial path; —establishing a routing of the signals between programmable chips using the physical resources available.Type: GrantFiled: July 26, 2016Date of Patent: November 14, 2017Assignee: Mentor Graphics CorporationInventors: Zied Marrakchi, Christophe Alexandre
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Publication number: 20170053052Abstract: The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of:—partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising:—inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips;—and the number of crossings of programmable chips of a critical combinatorial path;—establishing a routing of the signals between programmable chips using the physical resources available.Type: ApplicationFiled: July 26, 2016Publication date: February 23, 2017Applicant: Mentor Graphics CorporationInventors: Zied Marrakchi, Christophe Alexandre
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Patent number: 9400860Abstract: Technology is disclosed for designing a prototype including a plurality of programmable chips for modelling a logic design comprising a hierarchy of logic modules. An example method includes: creating a new hierarchy of logic modules on the basis of the hierarchy of the logic modules of the logic design, by flattening the modules that cannot be preserved according to design constraints; partitioning the new hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimizing: inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; and the number of crossings of programmable chips of a critical combinatorial path; and establishing a routing of the signals between programmable chips using the physical resources available.Type: GrantFiled: May 24, 2013Date of Patent: July 26, 2016Assignee: Mentor Graphics CorporationInventors: Zied Marrakchi, Christophe Alexandre
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Publication number: 20160161551Abstract: The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.Type: ApplicationFiled: July 8, 2014Publication date: June 9, 2016Applicant: Mentor Graphics CorporationInventors: Matthieu Tuna, Zied Marrakchi, Christophe Alexandre
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Publication number: 20150286761Abstract: The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of: —partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising: —inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; —and the number of crossings of programmable chips of a critical combinatorial path; —establishing a routing of the signals between programmable chips using the physical resources available.Type: ApplicationFiled: May 24, 2013Publication date: October 8, 2015Applicant: FLEXRAS TECHNOLOGIESInventors: Zied Marrakchi, Christophe Alexandre
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Patent number: 7795911Abstract: A switch box (2) for a programmable gate array including input ports grouping a plurality of inputs (I, I?) and output ports grouping a plurality of outputs (O, O?), with the inputs and the outputs being connected to a downstream connection tree structure from the inputs toward the outputs and including routing elements (4, 5, 6) organized according to several levels for connecting by a single path each input of all the input ports to at least one output of each output port. Switch boxes, logic units and programmable gate arrays including these, which are so arranged as to define a single path between two points of the array.Type: GrantFiled: September 15, 2008Date of Patent: September 14, 2010Assignees: Universite Pierre Et Marie Curie, Centre National de la Recherche ScientifiqueInventors: Zied Marrakchi, Hayder Mrabet, Habib Mehrez
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Publication number: 20100007378Abstract: A switch box (2) for a programmable gate array including input ports grouping a plurality of inputs (I, I?) and output ports grouping a plurality of outputs (O, O?), with the inputs and the outputs being connected to a downstream connection tree structure from the inputs toward the outputs and including routing elements (4, 5, 6) organized according to several levels for connecting by a single path each input of all the input ports to at least one output of each output port. Switch boxes, logic units and programmable gate arrays including these, which are so arranged as to define a single path between two points of the array.Type: ApplicationFiled: September 15, 2008Publication date: January 14, 2010Inventors: Zied MARRAKCHI, Hayder Mrabet, Habib Mehrez