Patents by Inventor Zih-Hsuan Huang

Zih-Hsuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157814
    Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.
    Type: Application
    Filed: December 22, 2020
    Publication date: May 19, 2022
    Inventors: Shi-You Liu, Ming-Shiou Hsieh, Zih-Hsuan Huang, Tsai-Yu Wen, Yu-Ren Wang
  • Patent number: 10644131
    Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Yu-Chien Sung
  • Publication number: 20190326414
    Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Yu-Chien Sung
  • Patent number: 10388756
    Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Yu-Chien Sung
  • Publication number: 20190221655
    Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Inventors: Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Yu-Chien Sung
  • Patent number: 9899498
    Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Chen Chan, Yi-Fan Li, Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Ming-Hua Chang, Yu-Shu Lin, Shu-Yen Chan
  • Publication number: 20180019324
    Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.
    Type: Application
    Filed: May 9, 2017
    Publication date: January 18, 2018
    Inventors: Tien-Chen Chan, Yi-Fan Li, Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Ming-Hua Chang, Yu-Shu Lin, Shu-Yen Chan
  • Patent number: 9680022
    Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Chen Chan, Yi-Fan Li, Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Ming-Hua Chang, Yu-Shu Lin, Shu-Yen Chan