Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.

Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.

Abstract: Systems and methods are disclosed herein for processing instructions in a processor pipeline to reduce the number of stalls therein. In an exemplary embodiment, a processor pipeline comprises a fetch stage configured to fetch instructions to be processed in the processor pipeline, a decode stage configured to decode the fetched instructions, and an execute stage configured to execute the decoded instructions. The decode stage may be configured to store instructions in a temporary buffer before the instructions are decoded. With this general structure, the decode stage can further stall the fetch stage if the execute stage detects an error caused by a change in the operational mode of the processor pipeline. An error may result, for example, when one or more registers being used in a current operational mode are determined to be inaccessible in a new operational mode.

Abstract: In a pipeline architecture, an instruction fault status register (FSR) is used to save the reason for a fault between the time an instruction is fetched and when it is executed. Sequential faults for different reasons cause an overwrite of the FSR and invalid abort codes upon the execution of an instruction. This method and system of updating the FSR passes the abort code with the instruction through the pipeline to the execute stage where the FSR is updated.