Patents by Inventor Zijian “Ray” Li
Zijian “Ray” Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11437485Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: GrantFiled: December 22, 2020Date of Patent: September 6, 2022Assignee: HRL LABORATORIES, LLCInventors: Yu Cao, Rongming Chu, Zijian Ray Li
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Publication number: 20210151578Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: ApplicationFiled: December 22, 2020Publication date: May 20, 2021Applicant: HRL Laboratories, LLCInventors: Yu CAO, Rongming CHU, Zijian "Ray" LI
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Patent number: 10916647Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: GrantFiled: January 31, 2019Date of Patent: February 9, 2021Assignee: HRL Laboratories, LLCInventors: Zijian “Ray” Li, Rongming Chu
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Patent number: 10903333Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: GrantFiled: July 28, 2017Date of Patent: January 26, 2021Assignee: HRL Laboratories, LLCInventors: Yu Cao, Rongming Chu, Zijian Ray Li
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Publication number: 20190165154Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Zijian "Ray" LI, Rongming CHU
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Patent number: 10263104Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: GrantFiled: April 25, 2014Date of Patent: April 16, 2019Assignee: HRL Laboratories, LLCInventors: Zijian “Ray” Li, Rongming Chu
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Patent number: 10134851Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: GrantFiled: December 14, 2017Date of Patent: November 20, 2018Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Yu Cao, Zijian “Ray” Li, Adam J. Williams
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Publication number: 20180114837Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: ApplicationFiled: December 14, 2017Publication date: April 26, 2018Inventors: Rongming Chu, Yu Cao, Zijian "Ray" Li, Adam J. Williams
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Publication number: 20180097081Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: ApplicationFiled: July 28, 2017Publication date: April 5, 2018Applicant: HRL Laboratories, LLCInventors: Yu CAO, Rongming CHU, Zijian Ray Li
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Patent number: 9812532Abstract: A field effect transistor includes a III-Nitride channel layer, a III-Nitride doped cap layer on the channel layer, a source electrode in contact with the III-Nitride cap layer, a drain electrode in contact with the III-Nitride cap layer, a gate electrode located between the source and the drain electrodes, and a gate dielectric layer between the gate electrode and the III-Nitride undoped channel layer, wherein the cap layer is doped to provide mobile holes, and wherein the gate dielectric layer comprises a layer of AlN in contact with the channel layer.Type: GrantFiled: August 28, 2015Date of Patent: November 7, 2017Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Yu Cao, Mary Y. Chen, Zijian “Ray” Li
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Publication number: 20170047453Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: ApplicationFiled: April 7, 2016Publication date: February 16, 2017Inventors: Rongming Chu, Yu Cao, Zijian "Ray" Li, Adam J. Williams
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Patent number: 9337332Abstract: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.Type: GrantFiled: May 29, 2014Date of Patent: May 10, 2016Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Mary Y. Chen, Xu Chen, Zijian “Ray” Li, Karim S. Boutros
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Publication number: 20150349117Abstract: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Inventors: Rongming CHU, Mary Y. Chen, Xu Chen, Zijian "Ray" Li, Karim S. Boutros
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Publication number: 20150311330Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: HRL Laboratories, LLCInventors: Zijian "Ray" LI, Rongming CHU
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Patent number: 8530978Abstract: A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET including a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact, and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.Type: GrantFiled: December 6, 2011Date of Patent: September 10, 2013Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Zijian “Ray” Li, Karim S. Boutros, Shawn Burnham