Abstract: Provided are a semiconductor device with decreased source and drain resistance and a manufacturing method. The semiconductor device includes a substrate and multiple three-dimensional semiconductor device arrays. The three-dimensional semiconductor device arrays are on the substrate, and the three-dimensional semiconductor device arrays are separated by isolation grooves. Each three-dimensional semiconductor device array includes a plurality of device layers in a vertical direction, each device layer includes a stack of a source/drain layer, a channel layer and a source/drain layer, and an end face of the source/drain layer adjacent to the isolation groove is metallized. The three-dimensional semiconductor device array further includes a plurality of gate stacks arranged in an array, the gate stack penetrates each device layer in the vertical direction and includes a gate material and a gate dielectric layer, and a device unit is defined at an intersection of the gate stack and the device layer.

Abstract: Provided are a NOR-type memory device, a manufacturing method, and an electronic device. The device includes: a plurality of gate stacks extending vertically on a substrate, wherein the gate stack includes a first gate conductor layer and a first filling layer; at least one device layer surrounding a periphery of the gate stack and extending along a sidewall of the gate stack; and a single-crystal vertical channel on a side of the device layer close to the gate stack and in contact with the first filling layer. At least one side surface of the gate stack in the vertical direction is a (100) or (110) crystal plane; and/or the body region includes a second filling layer or the body region includes a second gate conductor layer and a third filling layer, wherein at least one of first and third filling layers is a storage functional layer.