Patents by Inventor Zijun Sun

Zijun Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating semiconductor device
    Patent number: 11107723
    Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 31, 2021
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Long Wang, Zijun Sun, Chin-Chun Huang, Hailong Gu, Penghui Lu, Wen Yi Tan
  • Method of fabricating semiconductor device
    Publication number: 20210257249
    Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.
    Type: Application
    Filed: March 17, 2020
    Publication date: August 19, 2021
    Inventors: Long Wang, Zijun Sun, Chin-Chun Huang, Hailong Gu, Penghui Lu, WEN YI TAN