Abstract: The present disclosure provides a non-planar hole channel transistor and a fabrication method thereof. The non-planar hole channel transistor has a substrate, and a surface of the substrate has a step structure comprising a vertical surface. A non-planar channel layer is epitaxially grown laterally with the vertical surface as a core. A barrier layer is formed on the channel layer, so as to simultaneously form a two-dimensional hole gas and/or a two-dimensional electron gas at an interface between the barrier layer and the channel layer.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a groove formed on the substrate, a channel layer structure grown under restriction of the groove structure, the channel layer structure being exposed from an upper surface of the substrate; a barrier layer covering the exposed channel layer structure, a two-dimensional electron gas and a two-dimensional hole gas respectively formed on a second face and a first face of the channel layer structure, and a source, a gate, and a drain formed on the first face/second face of the channel layer structure, and a bottom electrode formed on the second face/first face of the channel layer structure.

Abstract: The present disclosure relates to a semiconductor device, comprising: a groove; a first channel layer positioned within the groove; and a first barrier layer positioned within the groove, wherein a first heterojunction having a vertical interface is included between the first channel layer and the first barrier layer and 2DEG or 2DHG is formed in the first heterojunction. The present disclosure also relates to a method of manufacturing a semiconductor device.

Abstract: A normally-closed device and a fabrication method thereof, relating to the technical field of semiconductors, is disclosed. The normally-closed device comprises a substrate, an epitaxial layer connected to the substrate comprising a first P-type nitride layer and a modified layer located on two sides of the first P-type nitride layer and formed by modifying a second P-type nitride layer in a preset region, where the first P-type nitride layer and the second P-type nitride layer are formed by epitaxially growing synchronously, a barrier layer connected to the first P-type nitride layer and the modified layer, a gate electrode connected to the barrier layer, and a source electrode and a drain electrode connected to the modified layer.

Abstract: The present disclosure provides an integrated circuit structure of a group III nitride semiconductor, a manufacturing method thereof, and use thereof. The integrated circuit structure is a complementary circuit of HEMT and HHMT based on the group III nitride semiconductor, and can realize the integration of HEMT and HHMT on the same substrate, and the HEMT and the HHMT respectively have a polarized junction with a vertical interface, the crystal orientations of the polarized junctions of the HEMT and the HHMT are different, the two-dimensional carrier gas forms a carrier channel in a direction parallel to the polarized junction, and corresponding channel carriers are almost depleted by burying the doped region.

Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes: a substrate including a vertical interface; a channel layer disposed outside the vertical interface; and a channel supply layer disposed outside the channel layer; wherein a vertical two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer.

Abstract: The present disclosure provides a semiconductor device, a manufacturing method, and electronic equipment. The semiconductor device including: a substrate; an interface, for generating two-dimensional charge carrier gas; a first electrode and a second electrode; and a first semiconductor layer of a first type doping formed on the substrate, wherein first regions and a second region are formed in the first semiconductor layer, wherein in the first regions, the dopant atoms of the first type do not have electrical activity, and in the second region, the dopant atoms of the first type have electrical activity; and the second region includes a portion coplanar with the first regions.

Abstract: A semiconductor device and a method of fabricating the same are proposed. The semiconductor device includes a plurality of hole-channel Group III nitride devices and a plurality of electron-channel Group III nitride devices. In the above, the hole-channel Group III nitride devices and the electron-channel Group III nitride devices are arranged in correspondence with each other. The electron-channel Group III nitride device has a fin-shaped channel, and a two-dimensional hole gas and/or a two-dimensional electron gas can be simultaneously formed at an interface between a compound semiconductor layer and a nitride semiconductor layer.

Abstract: The present invention relates to a semiconductor device, including: a first channel layer; a second channel layer; a first barrier layer, where a vertical first two-dimensional carrier gas is included at the position in the first channel layer close to an interface between the first channel layer and the first barrier layer; a second barrier layer, where a vertical second two-dimensional carrier gas is included at the position in the second channel layer close to an interface between the second channel layer and the second barrier layer, and the first channel layer and the second channel layer are located between the first barrier layer and the second barrier layer; a source electrode electrically connected to the first two-dimensional carrier gas and the second two-dimensional carrier gas; a drain electrode electrically connected to the first two-dimensional carrier gas and the second two-dimensional carrier gas; and a gate electrode located between the source electrode and the drain electrode, where the fir

Abstract: A filter (100) includes a piezoelectric layer (105); a first electrode (108), disposed at a first vertical face of the piezoelectric layer (105) and configured to receive an electric signal; and a second electrode (109), disposed at a second vertical face of the piezoelectric layer (105) and configured to output an electric signal, where the first vertical face and the second vertical face are two opposite sides of the piezoelectric layer (105).

Abstract: The present disclosure provides a driving circuit, a driving IC, and a driving system, relating to the technical field of electronic circuits. The driving circuit comprises a control module and a driving signal output module, the control module is electrically connected to the driving signal output module, and the driving signal output module is configured to be electrically connected to a to-be-driven device, wherein the driving signal output module comprises at least two transistors, and the at least two transistors are epitaxially grown on the same substrate; and the control module is configured to control a closed state of the at least two transistors, so as to control an operation state of the to-be-driven device.

Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes: a substrate including a vertical interface; a channel layer disposed outside the vertical interface; and a channel supply layer disposed outside the channel layer; wherein at least one of a vertical two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer.

Abstract: The present invention relates to a semiconductor device, including: a first channel layer, which includes a first channel region, a first gate doped region, and a second channel region, where the second channel region is located above the first channel region, and the first gate doped region is located between the first channel region and the second channel region; a first barrier layer, where a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode, which is located below the first gate doped region and in electric contact with the 2DEG or 2DHG in the first heterojunction; a second electrode, which is located above the first gate doped region and in electric contact with the 2DEG or 2DHG in the first heterojunction; and a third electrode, which is in electric contact, in the first gate doped region, with the 2DEG or 2DHG in the first heterojunction.

Abstract: A semiconductor device and a method of fabricating the same are proposed. The semiconductor device includes a plurality of hole-channel Group III nitride devices and a plurality of electron-channel Group III nitride devices. In the above, the hole-channel Group III nitride devices and the electron-channel Group III nitride devices are arranged in correspondence with each other. The electron-channel Group III nitride device has a fin-shaped channel, and a two-dimensional hole gas and/or a two-dimensional electron gas can be simultaneously formed at an interface between a compound semiconductor layer and a nitride semiconductor layer.

Abstract: The present disclosure provide a semiconductor device, a method for manufacturing a semiconductor device and an electronic apparatus. The device includes: a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer, the first semiconductor layer having a smaller band gap than the second semiconductor layer; a first electrode and a third electrode formed on the first or second semiconductor layer; a second electrode formed on the second semiconductor layer, and a third semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first channel layer; a first barrier layer, wherein a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode positioned on an upper side of the first heterojunction and configured to make electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the first electrode is connected to a first external voltage above the first heterojunction; and a second electrode positioned at a lower side of the first heterojunction and configured to make electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the second electrode is connected to a second external voltage below the first heterojunction.

Abstract: The present disclosure provides a semiconductor device, a manufacturing method, and electronic equipment. The semiconductor device comprising: a substrate; an interface, for generating two-dimensional charge carrier gas; a first electrode and a second electrode; and a first semiconductor layer of a first type doping formed on the substrate, wherein first regions and a second region are formed in the first semiconductor layer, wherein in the first regions, the dopant atoms of the first type do not have electrical activity, and in the second region, the dopant atoms of the first type have electrical activity; and the second region comprises a portion coplanar with the first regions. The semiconductor device can not only avoid damage to the crystal structure, but also can be easily realized in the processing, and it can maintain good transport properties of the two-dimensional charge carrier gas, which is beneficial to the improvement of device performance.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a groove formed on the substrate, a channel layer structure grown under restriction of the groove structure, the channel layer structure being exposed from an upper surface of the substrate; a barrier layer covering the exposed channel layer structure, a two-dimensional electron gas and a two-dimensional hole gas respectively formed on a second face and a first face of the channel layer structure, and a source, a gate, and a drain formed on the first face/second face of the channel layer structure, and a bottom electrode formed on the second face/first face of the channel layer structure.

Abstract: The present disclosure provides a driving circuit, a driving IC, and a driving system, relating to the technical field of electronic circuits. The driving circuit comprises a control module and a driving signal output module, the control module is electrically connected to the driving signal output module, and the driving signal output module is configured to be electrically connected to a to-be-driven device, wherein the driving signal output module comprises at least two transistors, and the at least two transistors are epitaxially grown on the same substrate; and the control module is configured to control a closed state of the at least two transistors, so as to control an operation state of the to-be-driven device.