Abstract: A light-emitting assembly and a vehicle are provided in the disclosure. The light-emitting assembly includes a light-transmitting member and a pattern layer. The pattern layer is attached to a surface of the light-transmitting member and includes multiple micro-patterns arranged at intervals. Each of the multiple micro-patterns has a radial size ranging from 0.025 mm to 0.26 mm, and a distance between each two adjacent micro-patterns ranges from 0.2 mm to 1.5 mm. When the light-emitting assembly is powered on, the multiple micro-patterns are configured to emit light to enable the pattern layer to be visible. The light-emitting assembly provided in the disclosure can enhance the vehicle interior atmosphere.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes a block of memory cells The peripheral circuitry can perform first program-verify loops in response to a first write operation to a first word line in a word line group to program memory cells associated with the first word line to multiple states. The word line group includes one or more word lines. Then, the peripheral circuitry determines verification start loops of the multiple states based on sensing results in the first program-verify loops, and performs second program-verify loops with the determined verification start loops of the multiple states in response to a second write operation to a second word line in the word line group.

Abstract: A semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes a block of memory cells The peripheral circuitry can perform first program-verify loops in response to a first write operation to a first word line in a word line group to program memory cells associated with the first word line to multiple states. The word line group includes one or more word lines. Then, the peripheral circuitry determines verification start loops of the multiple states based on sensing results in the first program-verify loops, and performs second program-verify loops with the determined verification start loops of the multiple states in response to a second write operation to a second word line in the word line group.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).