Patents by Inventor Zin-Chang Wei
Zin-Chang Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10113233Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.Type: GrantFiled: April 7, 2015Date of Patent: October 30, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo Fei Wang, Ming-Yu Fan, Jong-I Mou
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Publication number: 20170022611Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.Type: ApplicationFiled: April 7, 2015Publication date: January 26, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
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Patent number: 9105591Abstract: A method for forming a layer of material on a semiconductor wafer using a semiconductor furnace that includes a thermal reaction chamber having a heating system having a plurality of rotatable heaters for providing a heating zone with uniform temperature profile is provided. The method minimizes temperature variations within the thermal reaction chamber and promotes uniform thickness of the film deposited on the wafers.Type: GrantFiled: August 12, 2013Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zin-Chang Wei, Hsin-Hsien Wu, Chun-Lin Chang
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Publication number: 20150211122Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.Type: ApplicationFiled: April 7, 2015Publication date: July 30, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
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Patent number: 9023664Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.Type: GrantFiled: February 26, 2013Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
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Patent number: 8834671Abstract: A method and apparatus for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.Type: GrantFiled: April 1, 2013Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zin-Chang Wei, Tsung-Min Huang, Ming-Tsao Chiang, Cheng-Chen Calvin Hsueh
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Publication number: 20130330938Abstract: A method for forming a layer of material on a semiconductor wafer using a semiconductor furnace that includes a thermal reaction chamber having a heating system having a plurality of rotatable heaters for providing a heating zone with uniform temperature profile is provided. The method minimizes temperature variations within the thermal reaction chamber and promotes uniform thickness of the film deposited on the wafers.Type: ApplicationFiled: August 12, 2013Publication date: December 12, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zin-Chang WEI, Hsin-Hsien WU, Chun-Lin CHANG
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Patent number: 8536491Abstract: A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of rotatable heaters arranged and operative to heat the chamber. In one embodiment, spacing between the sidewall heaters is adjustable. The heating system controls temperature variations within the chamber and promotes uniform film deposit thickness on the wafers.Type: GrantFiled: March 24, 2009Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zin-Chang Wei, Hsin-Hsien Wu, Chun-Lin Chang
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Patent number: 8409997Abstract: A method and system for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.Type: GrantFiled: January 25, 2007Date of Patent: April 2, 2013Assignee: Taiwan Semiconductor Maufacturing Co., Ltd.Inventors: Zin-Chang Wei, Tsung-Min Huang, Ming-Tsao Chiang Chiang, Cheng-Chen Calvin Hsueh
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Patent number: 8404572Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.Type: GrantFiled: February 13, 2009Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
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Patent number: 8277286Abstract: A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case.Type: GrantFiled: February 13, 2009Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Ku Hung, Zin-Chang Wei, Huang Soon Kang, Chyi-Shyuan Chern
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Publication number: 20100291840Abstract: A chemical mechanical polishing (CMP) apparatus provides for polishing semiconductor wafers and for conditioning the polishing pad of the CMP apparatus using multiple conditioning disks at the same time. The conditioning disks may be moved together or independently along the surface of polishing pad to condition the entire surface of the rotating polishing pad.Type: ApplicationFiled: May 12, 2009Publication date: November 18, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Soon Kang HUANG, Kun-Ku HUNG, Zin-Chang WEI, Chyi Shyuan CHERN
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Publication number: 20100248496Abstract: A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of rotatable heaters arranged and operative to heat the chamber. In one embodiment, spacing between the sidewall heaters is adjustable. The heating system controls temperature variations within the chamber and promotes uniform film deposit thickness on the wafers.Type: ApplicationFiled: March 24, 2009Publication date: September 30, 2010Applicant: Talwan Semiconductor Manufacturing Co., Ltd.Inventors: Zin-Chang WEI, Hsin-Hsien Wu, Chun-Lin Chang
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Publication number: 20100210189Abstract: A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Ku Hung, Zin-Chang Wei, Huang Soon Kang, Chyi-Shyuan Chern
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Publication number: 20100210041Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
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Publication number: 20100181500Abstract: A method comprises pre-cooling a first semiconductor wafer outside of a process chamber, from a temperature at or above 15° C. to a temperature below 5° C. The pre-cooled first wafer is placed inside the process chamber after performing the pre-cooling step. A low-temperature ion implantation is performed on the first wafer after placing the first wafer.Type: ApplicationFiled: January 16, 2009Publication date: July 22, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Chang, Zin-Chang Wei, Hsin-Hsien Wu
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Patent number: 7732344Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.Type: GrantFiled: June 5, 2009Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Wen Tsai, Matt Yeh, Ming-Jun Wang, Shun Wu Lin, Chi-Chun Chen, Zin-Chang Wei, Chyi-Shyuan Chern
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Publication number: 20080179293Abstract: A method and system for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.Type: ApplicationFiled: January 25, 2007Publication date: July 31, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zin-Chang Wei, Tsung-Min Huang, Ming-Tsao Chiang, Cheng-Chen Calvin Hsueh
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Publication number: 20080047589Abstract: An apparatus for wafer cleaning includes an enclosure. A stage is within the enclosure. At least one first wall is within the enclosure, around the stage. A plate is within the enclosure and above the stage, operable to enclose a first region between the stage and the first wall. The apparatus further includes an exhauster fluidly coupled to the first region between the stage and the first wall.Type: ApplicationFiled: August 25, 2006Publication date: February 28, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Min Huang, Zin-Chang Wei, Ming-Tsao Chiang