Patents by Inventor Zin Sig Kim

Zin Sig Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10784179
    Abstract: A method for fabricating a semiconductor device includes sequentially laminating a separation layer and a first substrate layer on a sacrificial substrate, and forming a heat dissipation plate comprising a first region and a second region on the first substrate layer. The method further includes removing the sacrificial substrate and the separation layer, and patterning the first substrate layer to form a first substrate exposing the heat dissipation plate in the second region and contacting the heat dissipation plate in the first region, and forming a first element on the first substrate. The method still further includes forming a plurality of conductive pads disposed on the heat dissipation plate in the second region and a first line connecting at least one of the plurality of conductive pads to the first element, and forming a second element on the conductive pads in the second region.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: September 22, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyung Seok Lee, Zin-Sig Kim, Sung-Bum Bae
  • Publication number: 20200235028
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region and a second region, a first element disposed on the heat dissipation plate in the first region, and a second element disposed on the heat dissipation plate in the second region.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok LEE, Zin-Sig KIM, Sung-Bum BAE
  • Patent number: 10651107
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region and a second region, a first element disposed on the heat dissipation plate in the first region, and a second element disposed on the heat dissipation plate in the second region. The first element includes a first substrate, the second element includes a second substrate, the first substrate includes a material different from a material of the second substrate, the first substrate contacts the heat dissipation plate, and the second element is bonded to the heat dissipation plate in a flip-chip bonding manner.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 12, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok Lee, Zin-Sig Kim, Sung-Bum Bae
  • Publication number: 20190096782
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region and a second region, a first element disposed on the heat dissipation plate in the first region, and a second element disposed on the heat dissipation plate in the second region. The first element includes a first substrate, the second element includes a second substrate, the first substrate includes a material different from a material of the second substrate, the first substrate contacts the heat dissipation plate, and the second element is bonded to the heat dissipation plate in a flip-chip bonding manner.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 28, 2019
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok LEE, Zin-Sig KIM, Sung-Bum BAE
  • Patent number: 9899226
    Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Hae Cheon Kim, Jong Won Lim, Dong Min Kang, Yong Hwan Kwon, Seong Il Kim, Zin Sig Kim, Eun Soo Nam, Byoung Gue Min, Hyung Sup Yoon, Kyung Ho Lee, Jong Min Lee, Kyu Jun Cho
  • Patent number: 9755027
    Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 5, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok Lee, Ki Hwan Kim, Sang Choon Ko, Zin-Sig Kim, Jeho Na, Eun Soo Nam, Young Rak Park, Junbo Park, Chi hoon Jun, Dong Yun Jung
  • Publication number: 20170077282
    Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 16, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok LEE, Ki Hwan KIM, Sang Choon KO, Zin-Sig KIM, Jeho NA, EUN SOO NAM, Young Rak PARK, Junbo PARK, Chi Hoon JUN, Dong Yun JUNG
  • Publication number: 20160380119
    Abstract: A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region.
    Type: Application
    Filed: March 30, 2016
    Publication date: December 29, 2016
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong Yun JUNG, Hyun Soo LEE, Sang Choon KO, Jeong-Jin KIM, Zin-Sig KIM, Jeho NA, Eun Soo NAM, Jae Kyoung MUN, Young Rak PARK, Sung-Bum BAE, Hyung Seok LEE, Woojin CHANG, Hyungyu JANG, Chi Hoon JUN
  • Publication number: 20150380482
    Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
    Type: Application
    Filed: March 13, 2015
    Publication date: December 31, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun AHN, Hae Cheon KIM, Jong Won LIM, Dong Min KANG, Yong Hwan KWON, SEONG IL KIM, Zin Sig KIM, Eun Soo NAM, Byoung Gue MIN, Hyung Sup YOON, Kyung Ho LEE, Jong Min LEE, Kyu Jun CHO
  • Publication number: 20150194494
    Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 9, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ho Kyun AHN, Hae Cheon KIM, Zin Sig KIM, Sang Heung LEE, Byoung Gue MIN, Hyung Sup YOON, Dong Min KANG, Seong Il KIM, Jong Min LEE, Jong Won LIM, Yong Hwan KWON, Eun Soo NAM
  • Patent number: 9034239
    Abstract: Provided are fiber fabrication method and the fiber fabricated thereby. In this method, different monomer solutions are electrospun through nozzles whose outlets are stuck to each other and simultaneously interfacially polymerized to form a polymer fiber without a complicated process of preparing a polymer solution. Therefore, a polymer fiber can be simply prepared.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: May 19, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Ju Yun, Zin Sig Kim, Han Young Yu, Yark Yeon Kim, Won Ick Jang
  • Patent number: 8981937
    Abstract: An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: March 17, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Ji Man Park, Lee Mi Do, Kyu Ha Baek, Kun Sik Park, Dong Pyo Kim, Jong Chang Woo, Zin Sig Kim, Joo Yeon Kim, Ye Sul Jeong, Yong Hyun Ham
  • Patent number: 8939079
    Abstract: Disclosed are a printing plate and a mirror thereof, the printing plate including: printing portions for transferring an immersed solution, the printing portions being formed flat and arranged at regular intervals on one side of an upper part of the printing plate; and non-printing portions corresponding to a remaining area other than the printing portions, the non-printing portions being formed with at least two concavities and convexities respectively and arranged at regular intervals on the other side of the upper part of the printing plate.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: January 27, 2015
    Assignee: Intellectual Discovery Co., Ltd.
    Inventors: Joo Yeon Kim, Kyu-Ha Baek, Lee Mi Do, Ji Man Park, Kunsik Park, Zin Sig Kim, Dong-Pyo Kim, Ye Sul Jeong
  • Publication number: 20140166615
    Abstract: Mold structures for imprint lithography are provided. Mold chip patterns including patterns for nano structures are disposed on a mold substrate. A trench region is provided between the mold chip patterns. Protrusion portions protrude from a bottom surface of the trench region. The protrusion portions extend along the trench region in a plan view.
    Type: Application
    Filed: July 11, 2013
    Publication date: June 19, 2014
    Inventors: Zin Sig KIM, Hokyun Ahn
  • Patent number: 8673403
    Abstract: Provided is a method of forming a fine pattern of a polymer thin film using a phenomenon that another material having a large difference in surface energy in comparison with a polymer thin film pattern is dewetted on the polymer thin film pattern. Two polymer materials having a large difference in surface energy can be applied to readily and conveniently form a fine pattern of a polymer thin film of micrometer or sub-micrometer grade.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: March 18, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seong Hyun Kim, Sang Chul Lim, Yong Suk Yang, Zin Sig Kim, Doo Hyeb Youn
  • Publication number: 20130149532
    Abstract: Provided are fiber fabrication method and the fiber fabricated thereby. In this method, different monomer solutions are electrospun through nozzles whose outlets are stuck to each other and simultaneously interfacially polymerized to form a polymer fiber without a complicated process of preparing a polymer solution. Therefore, a polymer fiber can be simply prepared.
    Type: Application
    Filed: August 22, 2012
    Publication date: June 13, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Ju Yun, Zin Sig Kim, Han Young Yu, Yark Yeon Kim, Won Ick Jang
  • Patent number: 8404588
    Abstract: Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 26, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dong-Pyo Kim, Kyu-Ha Baek, Kunsik Park, Ji Man Park, Zin Sig Kim, Joo Yeon Kim, Ye Sul Jeong, Lee-Mi Do
  • Publication number: 20120164317
    Abstract: Provided is a method for fabricating a polarizer. The method includes forming an unevenness structure pattern on a substrate, coating conductive nano-particles on an entire surface of the unevenness structure pattern, and planarizing an entire surface of the resultant substrate after the conductive nano-particles are coated on the unevenness structure pattern.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 28, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Zin Sig KIM, Kyu Ha Baek, Lee Mi Do
  • Publication number: 20120161941
    Abstract: An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.
    Type: Application
    Filed: November 11, 2011
    Publication date: June 28, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ji Man PARK, Lee Mi DO, Kyu Ha BAEK, Kun Sik PARK, Dong Pyo KIM, Jong Chang WOO, Zin Sig KIM, Joo Yeon KIM, Ye Sul JEONG, Yong Hyun HAM
  • Publication number: 20120140350
    Abstract: Disclosed are a printing plate and a mirror thereof, the printing plate including: printing portions for transferring an immersed solution, the printing portions being formed flat and arranged at regular intervals on one side of an upper part of the printing plate; and non-printing portions corresponding to a remaining area other than the printing portions, the non-printing portions being formed with at least two concavities and convexities respectively and arranged at regular intervals on the other side of the upper part of the printing plate.
    Type: Application
    Filed: November 21, 2011
    Publication date: June 7, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Joo Yeon Kim, Kyu-Ha Baek, Lee Mi Do, Ji Man Park, Kunsik Park, Zin Sig Kim, Dong-Pyo Kim, Ye Sul Jeong