Abstract: Provided is a pH-sensitive membrane disruptive peptide having a structure as shown in formula (I) or a stereoisomer thereof or a pharmaceutically acceptable salt thereof, and a use thereof. The macromolecular material is hydrophobic and electrically neutral at normal physiological pH, and can self-assemble into nanoparticles with tight assembly and weak interaction with cell membranes. Under a slightly acidic pH condition, the macromolecular material can be protonated to form an amphiphilic structure composed of a hydrophobic domain and a cationic domain, which has strong interaction with the cell membranes and strong membrane disruptive activity, and thus can efficiently and highly selectively kill tumor cells.

Abstract: The present application relates to information storage technology and discloses a solid-state drive and a data access acceleration method thereof. The method comprises: establishing, in the solid-state drive, a mapping relationship between an application identifier and a storage subspace in the solid-state drive, wherein the application identifier is used to uniquely identify an application or a group of applications in a host; the solid-state drive receiving a write command from the host, the write command comprising the application identifier and data to be written; the solid-state drive determining a target storage subspace to be written to according to the mapping relationship and the application identifier in the write command; and the solid-state drive writing the data to be written into the target storage subspace. The method can significantly improve the write and read performance of the solid-state drive.

Abstract: The present application relates to the field of SSD and discloses an SSD device with dynamic capacity cache acceleration, comprising: a memory comprising multiple storage subspaces; a cache comprising multiple cache subspaces; a cache allocator configured to calculate a cache execution configuration based on a cache configuration request for the storage subspace; a cache executor which selects a traversal range and a traversal order based on a cache execution configuration, a structured data for traverse history and a virtual index of a storage unit, and calculates minimum and maximum cost thresholds, the traversal range includes a set of cache units in a corresponding cache subspace and is divided into a plurality of pending windows; traverses the pending windows in the traversal order, calculates a cost function for each cache unit in the current pending window based on a structured state table, and selects a cache unit with a cost function that is less than the minimum cost threshold.

Abstract: Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to Vref in the memory with decoding information generated during the decoding process.

Abstract: This application discloses a compression accelerator card, method of simulating hard disk mode to access the compression accelerator card.

Abstract: The present disclosure relates to methods and systems for evaluating a storage medium. The method may include receiving, via a user interface of a host, a user request to evaluate a storage medium coupled to a first controller. The method may also include determining whether there is a first binding history table associated with the storage medium stored in the host. In response to a determination that there is no first binding history table stored in the host, the method may include retrieving a binding history table from the storage medium via the first controller and determining the storage medium as a second-hand storage medium if there is at least one second controller different from the first controller in the binding history table.

Abstract: A method including determining that a memory unit is available for a channel for communication between a storage controller and a non-volatile storage device, the memory unit being for temporary storage for encoded data for transmission through the channel; allocating the memory unit to that channel; and updating a memory mapping entry corresponding to the memory unit. The memory mapping entry is stored in the storage controller. Updating a memory mapping entry may be based on reading/write tasks. The memory mapping entry may indicate a cross channel status, an operation mode and an identifier of the channel. The method may include determining the channel being stuck due to memory shortage and mapping more memory units to the channel.

Abstract: The present application relates to the field of SSD and discloses an SSD device with dynamic capacity cache acceleration, comprising: a memory comprising multiple storage subspaces; a cache comprising multiple cache subspaces; a cache allocator configured to calculate a cache execution configuration based on a cache configuration request for the storage subspace; a cache executor which selects a traversal range and a traversal order based on a cache execution configuration, a structured data for traverse history and a virtual index of a storage unit, and calculates minimum and maximum cost thresholds, the traversal range includes a set of cache units in a corresponding cache subspace and is divided into a plurality of pending windows; traverses the pending windows in the traversal order, calculates a cost function for each cache unit in the current pending window based on a structured state table, and selects a cache unit with a cost function that is less than the minimum cost threshold.

Abstract: This application discloses a compression accelerator card, method of simulating hard disk mode to access the compression accelerator card.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to Vref in the memory with decoding information generated during the decoding process.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to Vref with decoding information generated during the decoding process.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: The present disclosure relates to methods and systems for evaluating a storage medium. The method may include receiving, via a user interface of a host, a user request to evaluate a storage medium coupled to a first controller. The method may also include determining whether there is a first binding history table associated with the storage medium stored in the host. In response to a determination that there is no first binding history table stored in the host, the method may include retrieving a binding history table from the storage medium via the first controller and determining the storage medium as a second-hand storage medium if there is at least one second controller different from the first controller in the binding history table.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.