Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

Abstract: An embodiment of an apparatus may comprise a controller coupled to one or more substrates and including circuitry to control access to NVM with a destructive read characteristic, perform a first read of a codeword from the NVM at a first reference voltage of a low confidence zone, perform a second read of the codeword from the NVM at a second reference voltage of the low confidence zone, and assign a lower confidence value to bits of the codeword that have a different value for the first read of the codeword and the second read of the codeword as compared to a confidence value assigned to bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword. Other embodiments are disclosed and claimed.

Abstract: Examples relate to a Low-Density Parity-Check Code (LDPC) decoder apparatus or device, to an LDPC decoder system and to corresponding methods and computer programs. The LDPC decoder apparatus comprises input circuitry and processing circuitry. The processing circuitry is configured to obtain a syndrome of a codeword via the input circuitry. The processing circuitry is configured to perform LDPC iterative decoding using the obtained syndrome, wherein the changes to be applied to the codeword due to the LDPC iterative decoding are recorded by applying the changes to a surrogate codeword. The processing circuitry is configured to record changes to be applied to the codeword due to the LDPC iterative decoding by storing the surrogate codeword in a memory structure.

Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

Abstract: A memory controller to detect for an unintentional access to an incorrect location of a memory device and to provide error detection for data retrieved from an intended location of the memory device. In an embodiment, the memory controller services a read request, including retrieving data and an error correction code from a memory location. In another embodiment, the retrieved error correction code is evaluated, based on a combination of the retrieved data and an address identifier of the read request, to determine whether the address identifier of the read request corresponds to the memory location from which the data and error correction code were retrieved.