Patents by Inventor Zion Nahisi

Zion Nahisi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES
    Publication number: 20250007537
    Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.
    Type: Application
    Filed: September 17, 2024
    Publication date: January 2, 2025
    Applicant: Kioxia Corporation
    Inventors: Avi Steiner, Zion Nahisi, Ofir Kanter, Amir Nassie, Hanan Weingarten
  • Efficient decoding schemes for error correcting codes for memory devices
    Patent number: 12095481
    Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: September 17, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Avi Steiner, Zion Nahisi, Ofir Kanter, Amir Nassie, Hanan Weingarten
  • EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES
    Publication number: 20230253985
    Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.
    Type: Application
    Filed: January 27, 2022
    Publication date: August 10, 2023
    Applicant: Kioxia Corporation
    Inventors: Avi Steiner, Zion Nahisi, Ofir Kanter, Amir Nassie, Hanan Weingarten