Abstract: In this data processing device, a request for direct memory-access operation is detected as an interrupt signal. When such an interrupt is detected, a interrupt controller generates a vector corresponding to the interrupt sigal. On the basis of this vector, a DMA controller generates a control signal showing whether the interrupt signal is a normal interrupt or an interrupt for requesting the direct memory-access operation. A CPU includes a ROM for storing micro-code for achieving the direct memory-access operation. When the DMA controller generates a control signal corresponding to the interrupt signal, the CPU sequentially reads out the micro-codes, to execute the direct memory-access operation. Specifically, if an interrupt for requesting the direct memory-access operation is detected, different processing space from that used for a normal interrupt processing is accessed.