Abstract: In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer.

Abstract: In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer.

Abstract: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum layer overlying the dielectric layer. The aluminum layer has a predetermined roughness of greater than 20 Angstroms RMS. The method patterns the aluminum layer to expose portions of the dielectric layer. The method includes forming a second dielectric layer overlying the patterned aluminum layer and exposed portions of the dielectric layer. The method removes a portion of the second dielectric layer.

Abstract: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum layer overlying the dielectric layer. The aluminum layer has a predetermined roughness of greater than 20 Angstroms RMS. The method patterns the aluminum layer to expose portions of the dielectric layer. The method includes forming a second dielectric layer overlying the patterned aluminum layer and exposed portions of the dielectric layer. The method removes a portion of the second dielectric layer.