Patents by Inventor Zi-Song Wang

Zi-Song Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7341913
    Abstract: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the mask layer and the isolation structure and the mask layer together form a recession. A spacer is formed at the sidewall of the recession and the recession is filled with an insulating layer. The mask layer and the spacer are removed and a tunneling dielectric layer is formed over the substrate. A first conductive layer is formed to fill the first opening and the isolating layer is removed to form a second opening. A gate dielectric layer and a second conductive layer are formed over the substrate sequentially. The second conductive layer and the first conductive layer are patterned.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: March 11, 2008
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Zi-Song Wang
  • Publication number: 20070148861
    Abstract: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the mask layer and the isolation structure and the mask layer together form a recession. A spacer is formed at the sidewall of the recession and the recession is filled with an insulating layer. The mask layer and the spacer are removed and a tunneling dielectric layer is formed over the substrate. A first conductive layer is formed to fill the first opening and the isolating layer is removed to form a second opening. A gate dielectric layer and a second conductive layer are formed over the substrate sequentially. The second conductive layer and the first conductive layer are patterned.
    Type: Application
    Filed: March 10, 2006
    Publication date: June 28, 2007
    Inventor: Zi-Song Wang