Abstract: A controller handles host commands from a host processor and also interfaces the host processor to a serial device. Storage circuitry (e.g., a shift register) of the controller holds a predetermined plurality of data bits. State machine circuitry controls the storage circuitry for serial bit-level communication (e.g., using a PS/2 protocol) between the storage circuitry and the serial device. A processor executes code from a program memory. In particular, the program code causes the processor to detect that a host command has been received by the controller from the host processor and causes an action corresponding to the host command received. Because the processor is not involved with the serial bit-level communication between the storage circuitry and the serial device, the processor executing the software can handle host commands without affecting the serial bit-level communication.

Abstract: A CMOS ROM is fabricated and programmed using a two-metal fabrication process which is substantially equivalent to a conventionals CMOS polysilicon gate manufacturing technique so that the CMOS ROM is advantageously fabricated in the same process steps that are used to fabricate the other, non-ROM circuits on an integrated circuit chip. In this method, multiple bit-lines in a first metal layer are formed which overlie a substrate containing the array of transistors. The bit-lines are connected to drain regions of the transistors. A dielectric insulating layer is formed over the substrate and the bit-lines and the dielectric insulating layer is perforated by vias which allow connecting to the first metal layer. Multiple word-lines and multiple reference voltage lines are formed in a second metal layer overlying the dielectric insulating layer. Either a word-line or a reference voltage line is programmably selected to connect to the gate of a transistor for each transistor of the multiple transistors.

Abstract: A CMOS ROM is fabricated and programmed using a two-metal fabrication process which is substantially equivalent to a conventional CMOS polysilicon gate manufacturing technique so that the CMOS ROM is advantageously fabricated in the same process steps that are used to fabricate the other, non-ROM circuits on an integrated circuit chip. In this method, multiple bit-lines in a first metal layer are formed which overlie a substrate containing the array of transistors. The bit-lines are connected to drain regions of the transistors. A dielectric insulating layer is formed over the substrate and the bit-lines and the dielectric insulating layer is perforated by vias which allow connecting to the first metal layer. Multiple word-lines and multiple reference voltage lines are formed in a second metal layer overlying the dielectric insulating layer. Either a word-line or a reference voltage line is programmably selected to connect to the gate of a transistor for each transistor of the multiple transistors.

Abstract: A CMOS ROM is fabricated and programmed using a two-metal fabrication process which is substantially equivalent to a conventional CMOS polysilicon gate manufacturing technique so that the CMOS ROM is advantageously fabricated in the same process steps that are used to fabricate the other, non-ROM circuits on an integrated circuit chip. In this method, multiple bit-lines in a first metal layer are formed which overlie a substrate containing the array of transistors. The bit-lines are connected to drain regions of the transistors. A dielectric insulating layer is formed over the substrate and the bit-lines and the dielectric insulating layer is perforated by vias which allow connecting to the first metal layer. Multiple word-lines and multiple reference voltage lines are formed in a second metal layer overlying the dielectric insulating layer. Either a word-line or a reference voltage line is programmably selected to connect to the gate of a transistor for each transistor of the multiple transistors.