Abstract: A secured device includes an interface and a processor. The interface is configured to connect to a bus, to which a host and a second device are coupled. At least the second device operates over the bus in a slave mode, and the host operates on the bus as a bus master that initiates transactions on the bus, at least on behalf of the secured device. The processor is configured to request the host to initiate, for the secured device, a transaction that accesses the second device over the bus, to monitor one or more signals on the bus, at least within a period during which the host accesses the second device over the bus in performing the requested transaction, and to identify, based on the monitored signals, whether a security violation occurred in performing the requested transaction.

Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves one or more peripheral devices, at least one of the peripheral devices being a memory device. The processor is connected to the bus in addition to the peripheral devices, and is configured to hold a definition that distinguishes between authorized and unauthorized transactions with the memory device, to identify on the bus a transaction in which a bus-master device attempts to access the memory device, and to initiate a responsive action in response to identifying that the transaction is unauthorized in accordance with the definition.

Abstract: An apparatus includes an electronic circuit, a keypad and an active-shield layer. The keypad includes one or more keys for entering data to the electronic circuit by a user. The active-shield layer is placed between the electronic circuit and the keypad, and includes one or more electrical conductors laid in a pattern that shields at least a portion of the electronic circuit. In a specified region, the one or more electrical conductors of the active-shield layer are shaped to form contacts for sensing the one or more keys.

Abstract: An electronic circuit for Random Number Generation (RNG) includes a first inverter having a first input and a first output, and a second inverter having a second input and a second output. The first output is connected to the second input, and the second output is connected to the first input. A switch is configured to (i) when closed, to set the first and second inverters to a meta-stable state by shorting the first output to the first input and the second output to the second input, and (ii) when open, to release the first and second inverters from the meta-stable state to a bi-stable random state. Logic circuitry is configured to alternately close and open the switch, and to output random values from at least one of the first and second inverters when at the bi-stable random state.

Abstract: In one embodiment, a protected system, includes a first apparatus disposed on a silicon chip, and to perform a functional process, a second apparatus disposed on the silicon chip, and to perform a protecting process having a verifiable test result, the first and the second apparatus having a physical layout which interleaves at least part of the first apparatus with at least part of the second apparatus so that an attack on the at least part of the first apparatus also attacks the at least part of the second apparatus, a primary controller to signal the second apparatus to perform the protecting process during a time period that the first apparatus is performing the functional process, and an attack handling controller to perform a protective action to protect the functional process responsively to the protecting process failing to verify the verifiable test result providing an indication that the attack is being performed.

Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves a host device and a non-volatile memory (NVM) device. The processor is connected to the bus in addition to the host device and the NVM device. The processor is configured to detect on the bus a boot process, in which the host device retrieves boot code from the NVM device, and to ascertain a security of the boot process, based on an authentic copy of at least part of the boot code of the host device.

Abstract: An electronic device includes a combinational logic circuit, one or more state-sampling components, and protection circuitry. The combinational logic circuit has one or more inputs and one or more outputs. The state-sampling components are configured to sample the outputs of the combinational logic circuit at successive clock cycles. The protection circuitry is configured to protect the combinational logic circuit by, per clock cycle, starting to apply random data to the inputs of the combinational logic circuit a given time duration before a sampling time of the state-sampling components for that clock cycle, and, after applying the random data, switching to apply functional data to the inputs of the combinational logic circuit, to be sampled by the state-sampling components. A propagation delay, over any signal path via the combinational logic circuit, is no less than the given time duration.

Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves one or more peripheral devices, at least one of the peripheral devices being a memory device. The processor is connected to the bus in addition to the peripheral devices, and is configured to hold a definition that distinguishes between authorized and unauthorized transactions with the memory device, to identify on the bus a transaction in which a bus-master device attempts to access the memory device, and to initiate a responsive action in response to identifying that the transaction is unauthorized in accordance with the definition.

Abstract: A system for improving utilization of a nonvolatile flash memory device which has pages whose guaranteed per-cycle erase time and guaranteed number of cycles are known, the system comprising erase time determination functionality for individual pages; de-facto total erase-time accumulation functionality incrementing, for each erase cycle to which an individual page is subjected, by the individual page's de facto erase time per cycle as provided by the erase time measurement functionality; and flash memory page usage monitoring functionality operative to control usage of pages in flash memory including selecting at least one individual flash memory page depending on a comparison between the individual flash memory page's de facto total erase time and a guaranteed erase time computed as a product of the guaranteed per-cycle erase time and of the guaranteed number of cycles.

Abstract: A method for initializing a computer system, which includes a Central Processing Unit (CPU), a Trusted Root Device and a Trusted Platform Module (TPM), includes authenticating a boot code of the CPU using the Trusted Root Device, and booting the CPU using the authenticated boot code. A challenge-response transaction, in which the TPM authenticates the Trusted Root Device, is initiated by the CPU following booting of the CPU. Only in response to successful authentication of the Trusted Root Device using the challenge-response transaction, a resource used in operating the computer system is released from the TPM.

Abstract: A controller includes a host interface and a processor. The host interface is configured for communicating with a host. The processor is configured to receive from the host, via the host interface, instructions for execution in a Non-Volatile Memory (NVM), to identify among the instructions an instruction, which pertains to a secure monotonic counter and is intended for execution in an NVM having a secure monotonic counter embedded therein, and to execute the identified instruction, and respond to the host responsively to the instruction, instead of the NVM.

Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves one or more peripheral devices. The bus includes (i) one or more dedicated signals that are each dedicated to a respective one of the peripheral devices, and (ii) one or more shared signals that are shared among the peripheral devices served by the bus. The processor is connected to the bus as an additional device in addition to the peripheral devices, and is configured to disrupt on the bus a transaction in which a bus-master device attempts to access a given peripheral device, by disrupting a dedicated signal associated with the given peripheral device.

Abstract: An apparatus includes an electronic circuit, a keypad and an active-shield layer. The keypad includes one or more keys for entering data to the electronic circuit by a user. The active-shield layer is placed between the electronic circuit and the keypad, and includes one or more electrical conductors laid in a pattern that shields at least a portion of the electronic circuit. In a specified region, the one or more electrical conductors of the active-shield layer are shaped to form contacts for sensing the one or more keys.

Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves a host device and a non-volatile memory (NVM) device. The processor is connected to the bus in addition to the host device and the NVM device. The processor is configured to detect on the bus a boot process, in which the host device retrieves boot code from the NVM device, and to ascertain a security of the boot process, based on an authentic copy of at least part of the boot code of the host device.

Abstract: A secured device includes an interface and a processor. The interface is configured to connect to a bus, to which a host and a second device are coupled. At least the second device operates over the bus in a slave mode, and the host operates on the bus as a bus master that initiates transactions on the bus, at least on behalf of the secured device. The processor is configured to request the host to initiate, for the secured device, a transaction that accesses the second device over the bus, to monitor one or more signals on the bus, at least within a period during which the host accesses the second device over the bus in performing the requested transaction, and to identify, based on the monitored signals, whether a security violation occurred in performing the requested transaction.

Abstract: An apparatus includes a memory, an interface and read restriction logic. The read restriction logic is configured to receive via the interface a request to read a data value from a specified address of the memory, to retrieve the data value from the specified address, to check, upon finding that the specified address falls in an address range that is predefined as restricted, whether the retrieved data value belongs to a predefined set of permitted data values, to respond to the request with the retrieved data value when the retrieved data value belongs to the set of permitted data values, and, otherwise, when the retrieved data value does not belong to the set of permitted data values, to respond to the request with a dummy data value.

Abstract: An apparatus includes a memory, an interface and read restriction logic. The read restriction logic is configured to receive via the interface a request to read a data value from a specified address of the memory, to retrieve the data value from the specified address, to check, upon finding that the specified address falls in an address range that is predefined as restricted, whether the retrieved data value belongs to a predefined set of permitted data values, to respond to the request with the retrieved data value when the retrieved data value belongs to the set of permitted data values, and, otherwise, when the retrieved data value does not belong to the set of permitted data values, to respond to the request with a dummy data value.

Abstract: A method in a security device that provides a security service to a host includes receiving a security command from an application program running on the host. The security command is executed by accessing a Non-Volatile Memory (NVM) device external to the security device transparently to the application program via a dedicated device driver, which runs on the host and mediates between the NVM device and the security device.

Abstract: An apparatus includes a Non-Volatile Memory (NVM) and a controller. The controller is configured to store in the NVM a state array, which includes multiple words. In each word, one or more bits are designated as lock-bits. The controller is further configured to set an operational state for the apparatus based on the lock-bits of the state array, by (i) deciding whether each word in the state array is locked or unlocked by comparing the lock-bits of that word to respective expected lock values, (ii) if all the words in the state array are found locked, setting the apparatus to a locked state, (iii) if all the words in the state array are found unlocked, setting the apparatus to an unlocked state, and (iv) if one or more of the words are found locked and one or more other words are found unlocked, setting the apparatus to an error state.

Abstract: An apparatus includes a Non-Volatile Memory (NVM) and a controller. The controller is configured to store in the NVM a state array, which includes multiple words. In each word, one or more bits are designated as lock-bits. The controller is further configured to set an operational state for the apparatus based on the lock-bits of the state array, by (i) deciding whether each word in the state array is locked or unlocked by comparing the lock-bits of that word to respective expected lock values, (ii) if all the words in the state array are found locked, setting the apparatus to a locked state, (iii) if all the words in the state array are found unlocked, setting the apparatus to an unlocked state, and (iv) if one or more of the words are found locked and one or more other words are found unlocked, setting the apparatus to an error state.