Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: The circuits and methods described herein provide technical solutions for technical problems facing USB links. To reduce or eliminate effects associated with a USB link entering a low-power mode, initial link acquisition may be performed while the spread-spectrum-clocking (SSC) modulation is disabled. Following the initial link acquisition, the SSC modulation may be enabled dynamically in a later stage. This delayed enablement of the re-timers provides improved performance over solutions in which the SSC modulation is constantly enabled, including reducing the complexity of the timing training process and enabling a faster USB link re-establishment. This reduced link acquisition period may enable the system to enter power saving modes more frequently, and may reduce latency involved in exiting power saving modes. This may maintain or improve total USB transmission speeds and may reduce USB-related power consumption for USB connected devices.

Abstract: One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

Abstract: One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.

Abstract: An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.

Abstract: In one embodiment, an apparatus includes a host controller to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect for a plurality of devices. The host controller is to monitor control plane messages on the interconnect, detect, in the control plane messages, a power state change command for a device coupled to the interconnect, wherein the devices utilizes a tunneled protocol on the interconnect, and modify power distribution for one or more other devices of the interconnect based on detecting the power state change command.

Abstract: A system can include a host router comprising connection manager logic, a display port adapter, and a display port adapter register to comprise display port adapter register values. A display port source device comprises a display port transmitter connected to the display port adapter. A display port configuration data (DPCD) register comprises display port configuration register values for the display port, the display port transmitter to write to the DPCD register. The display port adapter is to map DPCD register values to the display port adapter register. The connection manager logic is to receive a notification message requesting bandwidth allocation for the display port transmitter, determine an allocated bandwidth for the display port transmitter, and write the allocated bandwidth into the display port adapter register.

Abstract: A universal serial bus (USB) router can include a display port input device to receive a display port signal. The display port input device can include display port link layer parser circuitry to identify display port control or data information from the received display port signal, USB packet construction circuitry to construct a USB packet comprising the display port control or data information identified by the display port link layer parser circuitry, and a USB switch to transmit the USB packet comprising the display control or data information over a USB link. A display port output device can include display port packetizer circuitry to construct a display port packet from the display port control or data information from the USB packet, and display port output circuitry to output the display port packet across a display port link.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: An apparatus for enabling simultaneous multimedia content and user data streaming from a handheld device to a display device is disclosed. The apparatus enables power charging of the handheld device while streaming the multimedia content and the user data from the handheld device. The apparatus comprises a data-multimedia-power interface (DMPI) connector installed in the handheld device and designed to enable the transport of at least high definition multimedia signals, data signals, a power signal, and control signals between the handheld device and the display device; and a DMPI circuit for multiplexing the high definition multimedia signals with the data signals, to enable simultaneous streaming of the respective multimedia content and the user data to the display device, wherein the DMPI circuit further extracts a power signal from the display device for power charging of the display device.

Abstract: An apparatus for enabling simultaneous multimedia content streaming and power charging of handheld devices, comprises a universal connector installed in a first device and enables connectivity of at least one multimedia display interface and at least one data interface with a second device, the first device is connected to the second device using a charging-streaming cable having, at one end, a first connector compliant with the universal connector, and at the other end, a second connector compliant with a multimedia display interface and a third connector compliant with a data interface of the second device, wherein streaming of the multimedia content is from the universal connector in the first device to the second connector in the second device and power charging of the first device is through the third connector of the second device; and a detector for determining a type of the multimedia display interface of the second device.

Abstract: A multimedia interface cable for achieving complete interoperability between different types of multimedia display interfaces. The cable comprises a first multimedia connector including a plurality of contact pins of at least high-speed multimedia signals and control signals; a second multimedia connector including a plurality of contact pins of least high-speed multimedia signals and control signals; a plurality of un-crossing conducting wires for coupling the plurality of contact pins of the high-speed multimedia signals in the first multimedia connector to the plurality of contact pins of the high-speed multimedia signals in the second multimedia connector; and a plurality of conducting wires for coupling the plurality of contact pins of the control signals in the first multimedia connector to the plurality of contact pins of the control signals in the second multimedia connector.

Abstract: A triple-mode connectivity apparatus for enabling interoperability between a multimedia display interface and a data interface. The apparatus comprises a universal connector installed in a first device and structured to enable connectivity between the multimedia display interface and the data interface of a second device, the first device is connected to the second device using a cable having a first connector compliant with the universal connector and a second connecter compliant with the data interface of the second device; a physical layer interface for processing signals compliant with the multimedia display interface and the data interface; and a detector for detecting an interface type of the second device and setting the apparatus to process signals according to the determined interface type.