Patents by Inventor Ziwei Yu

Ziwei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118638
    Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Jian Yin, Lin Chen, Ziwei Yu, Xiaobin Wang, Zhiqiang Niu, Kuan-Hung Li
  • Patent number: 12015336
    Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: June 18, 2024
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Ziwei Yu, Lin Chen, Zhiqiang Niu
  • Publication number: 20230412070
    Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Ziwei Yu, Lin Chen, Zhiqiang Niu
  • Patent number: 11750089
    Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: September 5, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Ziwei Yu, Lin Chen, Zhiqiang Niu
  • Publication number: 20230137176
    Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Ziwei Yu, Lin Chen, Zhiqiang Niu