Abstract: This application provides an object processing method, an electronic device, and a storage medium. In the method, when an electronic device displays a first interface, the electronic device may be triggered, by using a gesture, to display a multi-layer interface. A partial area of an image of the first interface is displayed in a left-side area of the multi-layer interface, one or more application icons are displayed in a right-side area, and one or more objects are displayed in a middle area. A user drags the object to an area above the partial area of the image of the first interface, to trigger the electronic device to display another interface of an application. The user may alternatively drag the object to an area above the application icon, to trigger the electronic device to display an interface of the application. The interface displays content related to the object.

Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.

Abstract: A control method and an apparatus for a power supply system, and a power supply system are provided. The control method includes: obtaining a current SOC and current charging/discharging power of the energy storage apparatus connected to the first power supply device; and executing a target control policy, in response to the current SOC exceeding a target SOC range, or the current charging/discharging power exceeding a target power range. The executing the target control policy includes: controlling a frequency of the first power supply device; or controlling a contactor connected to the second power supply device to be disconnected, to disconnect the second power supply device from the coupling point.

Abstract: A switch device includes a first transistor, a second transistor, a first driver, and a second driver. The first transistor includes a first terminal, a second terminal, and a control terminal. The second transistor includes a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the first transistor, and a control terminal. The first driver is coupled to the control terminal of the first transistor and configured to drive the first transistor. The second driver is coupled to the control terminal of the second transistor and configured to drive the second transistor. During a first period in which the first transistor and the second transistor are to be turned on, the first transistor is turned on before the second transistor is turned on.

Abstract: The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

Abstract: Apparatus and associated methods relate to a gate drive timing controller (GDTC). In an illustrative example, the GDTC may generate a power stage activation signal (PSAS) to control an output current of a MOSFET(s) of the power stage. Three pullup transistors, for example, may be electrically connected to the control output in parallel, configured to generate the PSAS as a function of a switch node voltage (Vsw) and a source inductance voltage (VLS) of the MOSFET. For example, a first pullup transistor may be activated when a PWM signal for the power stage is received, and deactivated based on the VLS. For example, a second pullup transistor may be synchronized with the PWM signal. For example, a third pullup transistor may be activated when the Vsw is detected. Various embodiments may advantageously generate the PSAS adaptively to reduce turn-on loss of the MOSFET while keeping a low transient voltage spike.

Abstract: Apparatus and associated methods relate to a gate drive timing controller (GDTC). In an illustrative example, the GDTC may include a control output configured to generate a power stage activation signal (PSAS) to control a power stage output. For example, the control output may be operably coupled to a switch device having a power MOSFET for delivering power and a sense FET. In some embodiments, the GDTC may include a timing control logic (TCL) configured to generate the PSAS. For example, the TCL may include three pullup transistors and three pulldown transistors. For example, gate terminals of the three pullup transistors and the three pulldown transistors are separately controlled by the TCL as a function of the sense voltage related to a source voltage of the power MOSFET. Various embodiments may advantageously allow an adaptive generation of the PSAS based on a sensed output current from the power MOSFET.

Abstract: Provided are a voltage modulation method and a three-level inverter, belonging to the field of inverter control technologies. The voltage modulation method is applied to a three-level inverter circuit including a neutral line relay. The voltage modulation method includes: determining a desired output voltage for each phase of the three-level inverter circuit; obtaining, in response to the neutral line relay being in an on state, a positive half-bus voltage and a negative half-bus voltage in the three-level inverter circuit; determining, based on the positive half-bus voltage and the desired output voltage, a first switching duty cycle during a positive half-cycle; determining, based on the negative half-bus voltage and the desired output voltage, a second switching duty cycle during a negative half-cycle; and driving, based on the first switching duty cycle and the second switching duty cycle, the three-level inverter circuit to output the desired output voltage.

Abstract: An electronic device may directly display a plurality of application service icons in an interface in response to an operation performed by a user on information, so as to help the user place the information into a target application service, so that the electronic device can efficiently and quickly complete information transmission between applications, thereby effectively reducing an operation step required by the user to complete information transmission across applications, improving interaction efficiency between the user and the electronic device, and further improving user experience.

Abstract: This application provides a cross-application data transmission method and a related device. An electronic device that implements the cross-application data transmission method, such as a mobile phone or a tablet computer, may obtain data such as a picture or a text from a currently displayed interface. After detecting that a user drags the data into a preset hot zone, the electronic device determines one or more applications capable of receiving the data. After detecting an operation of continuing dragging, by the user, the data into a region in which any application icon is located and releasing the data, the electronic device may send the data to a corresponding application, thereby providing the user with a quick and convenient cross-application data transmission service.

Abstract: The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.

Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.

Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.

Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.

Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.