Abstract: A method for reckoning the environmental background water temperature and calculating the temperature rise in a temperature rise area of a newly-built coastal power plant is provided. The reckoning method includes: S01, before an operation of the newly-built coastal power plant, building a water temperature reference station; S02, continuously observing and recording water temperature data of the water temperature reference station and other water temperature observation stations; S03, analyzing the water temperature data obtained in S02; and S04, reckoning a sea surface natural water temperature of the other water temperature observation stations.

Abstract: In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 ?, respectively, so as to realize the flatness of the silicon-on-insulator film.

Abstract: Provided herein are an indene compound, e.g., a compound of Formula (I), and a pharmaceutical composition thereof. Also provided herein is a method of their use for treating, preventing, or ameliorating one or more symptoms of a fibrotic disease.

Abstract: A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 ?, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

Abstract: A screw compressor slide valve with gas pulsation attenuation function includes valve walls and internal through holes. A screw compressor includes the screw compressor slide valve. A part of exhausted gas of the screw compressor is directly discharged from an exhaust port to an exhaust chamber to form a main exhaust flow channel; another part of the exhausted gas is discharged from the exhaust port into the exhaust chamber after being delayed by the internal through holes, which forms a branched exhaust flow channel. Since the branched exhaust flow channel is longer than the main exhaust flow channel, when the gas pulsation in the branched exhaust flow channel lags behind that in the main exhaust flow channel by 180-degree in phase, two gas pulsations in the two flow channels are offset due to opposite gas pulsation phases, which attenuates the gas pulsation, thereby suppressing induced vibration and noise.

Abstract: An advanced manufactured transwell (AM-transwell), the AM-transwell comprises: a lower chamber; an upper chamber; a membrane disposed between the lower chamber and the upper chamber; and one or more legs. The one or more legs form at least a portion of the lower chamber. One or more of the lower chambers, the upper chamber, the membrane and the one or more legs is printed using a synthetic bioink. Methods for making and using the AM-transwell are also disclosed.

Abstract: The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

Abstract: A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

Abstract: The present application provides a process of surface treatment of a silicon-on-insulator (SOI) wafer comprising: providing a SOI wafer comprising a back substrate, a top silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; conducting a first planarization to a surface of the top silicon layer by conducting a batch annealing process at a first target temperature, and conducting a second planarization to a surface of the top silicon layer by conducting a rapid thermal annealing process at a second target temperature. The present application combines the batch annealing process and the rapid thermal annealing process to optimize the SOI wafer, especially the surface roughness of the SOI wafer. The SOI wafer planarized by the two thermal annealing processes has a good surface roughness of the top silicon layer which satisfies process requirements.

Abstract: The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon.

Abstract: A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

Abstract: Disclosed are an oxazoline compound, a synthesis method therefor and an application thereof. The oxazoline compound has a structure represented by formula (I), wherein in the formula (I), R is selected from groups represented by formula (I-1), formula (I-2), and formula (I-3), where an oxazoline derivative having a novel molecular structure is obtained by introducing a nitrogen heterocycle, an ether bond or a sulfonate structure into the oxazoline compound. The oxazoline derivative is useful in the field of agricultural protection, and has higher acaricidal activity than etoxazole, can inhibit the synthesis of chitin from mites, and can effectively control the embryogenesis and development of eggs of Tetranychus cinnabarinus, as well as the ecdysis process from larvae to adults, and therefore has a significant effect in killing mite eggs and larvae.

Abstract: The present invention belongs to the technical field of pesticides, particularly relates to sulfonyl-structure-containing triazinone derivatives, their preparation methods, and their uses in insect killing and/or bacterium killing. The sulfonyl-structure-containing triazinone derivatives are compounds represented by formula (Ia) or (Ib). The sulfonyl-structure-containing triazinone derivatives provided in the present invention exhibit outstanding insecticidal activity as well as bactericidal activity.

Abstract: The present invention belongs to the technical field of pesticides, particularly relates to sulfonyl-structure-containing triazinone derivatives, their preparation methods, and their uses in insect killing and/or bacterium killing. The sulfonyl-structure-containing triazinone derivatives are compounds represented by formula (Ia) or (Ib). The sulfonyl-structure-containing triazinone derivatives provided in the present invention exhibit outstanding insecticidal activity as well as bactericidal activity.