Abstract: Secondary battery and preparation method thereof are provided. Lithium source, iron source, phosphorus source, transition metal salt source, bismuth source, and solvent are mixed to obtain intermediate solution. PH of intermediate solution ranges from 1.0 to 4.0. Intermediate solution is subjected to hydrothermal reaction, to obtain precursor by drying. Precursor is subjected to heat treatment to obtain core. Core includes lithium iron phosphate and bismuth salt. Core is coated with coating material to obtain cathode material. Cathode material includes core and conductive polymer coating layer arranged on at least surface of core. Finally, cathode material is prepared into secondary battery. Cathode material in present disclosure has advantages of high compaction density and high conductivity, which can significantly enhance energy density, cycle performance, and high-and-low temperature performance when cathode material is applied to secondary battery.

Abstract: Disclosed is a method for preparing lithium-ion batteries including: winding or sheet-stacking a positive electrode sheet, a negative electrode sheet, and a separator, and then placing them into a case to form an initial cell; injecting a first electrolyte into the initial cell, where the first electrolyte includes: 0.5 wt % to 2 wt % vinylene carbonate, 5 wt % to 15 wt % lithium salt, and non-aqueous organic solvent (all by weight); performing a formation process on the initial cell to form an initial solid electrolyte interphase film; injecting a second electrolyte into the initial cell, where the second electrolyte includes: 5 wt % to 20 wt % vinylene carbonate, 5 wt % to 15 wt % lithium salt, 0.005 wt % to 30 wt % infiltrant stabilizer, and non-aqueous organic solvent (all by weight); where the first electrolyte or the second electrolyte further includes: at least one of 1,3-propane sultone or fluoroethylene carbonate.

Abstract: A low-noise amplifier (LNA) includes a first transistor, a first source inductor coupled to a source of the first transistor, and a second transistor, wherein a source of the second transistor is coupled to a drain of the first transistor, a gate of the second transistor is coupled to a bias circuit, and a drain of the second transistor is coupled to an output of the LNA. The LNA also includes an output inductor coupled between a supply rail and the output of the LNA, wherein the output inductor is magnetically coupled with the first source inductor.

Abstract: Provided is a method for preparing a secondary battery including a battery cell. The secondary battery includes a negative electrode. The method includes: preparing a negative electrode slurry, coating the negative electrode slurry on the negative current collector, and then drying and compacting the negative electrode slurry to form a negative electrode material coating, thereby obtaining the negative electrode. Preparing the negative electrode slurry includes: dry blending a negative electrode active material, a conductive agent and a dispersant to obtain a dry blend; kneading the dry blend with a part of the first solvent to obtain a kneaded material; subjecting the kneaded material, the remaining part of the first solvent, the second solvent to a first wet blending to obtain a first wet blend; and subjecting the first wet blend, a thickener and a binder to a second wet blending to obtain the negative electrode slurry.

Abstract: Embodiments of the present disclosure relate to the field of energy storage and provide a method for manufacturing sodium-ion rechargeable batteries. The method includes: providing a cell and disposing the cell inside a casing; performing a first injection operation on the cell disposed inside the casing using a first electrolyte, where the first electrolyte includes: 1,3-propanesultone of 0.5 wt % to 2 wt %, tris(trimethylsilyl) phosphate of 0.1 wt % to 2 wt %, fluoroethylene carbonate of 0.1 wt % to 2 wt %, a film forming additive of 0.01 wt % to 5 wt %, and at least one sodium salt; performing infiltration treatment and pre-charging treatment; performing a second injection operation on the cell disposed inside the casing using a second electrolyte, where the second electrolyte includes: 1,3-propanesultone of 5 wt % to 20 wt %, a nitriles compound of 3 wt % to 30 wt %, a water and acid removing additive of 0.005 wt % to 30 wt %, and at least one sodium salt; and allowing the cell to stand.

Abstract: A Cathode material and a preparation method therefor and use thereof are provided. The cathode material includes a cathode active substrate, and a surface of the cathode active substrate is coated with a carbon coating layer, wherein a surface of the carbon coating layer has an esterophilic group. The invention changes the surface energy of the carbon coating layer by introducing the esterophilic carbonyl to the surface of the carbon coating layer of the cathode active substrate, thereby significantly improving the wettability of the cathode active particles to the electrolyte. Moreover, the bulk structure of the active material is not changed, so the electrochemical performance of the cathode active material is guaranteed. The cathode plate prepared by the invention shows excellent wettability in the electrolyte, and a prepared battery shows low internal resistance, high energy efficiency and other characteristics.

Abstract: A method for preparing an energy storage cell is provided, and includes: providing a film layer, where the film layer is one of a positive electrode sheet, a separating film, and a negative electrode sheet, and the film layer has a first edge and a second edge opposite the first edge; performing a dispensing treatment on the film layer to form a plurality of groups of glue dots arranged on a surface of the film layer in a first direction; providing remaining two of the positive electrode sheet, the separating film, and the negative electrode sheet, and stacking the negative electrode sheet, the separating film, and the positive electrode sheet sequentially to form a stacked structure; and performing a winding treatment on the stacked structure from the second edge toward the first edge.

Abstract: Disclosed are a battery charging method, a battery charging device, and a battery charging apparatus. The battery charging method, comprising: determining a direct current resistance (DCR) curve of a rechargeable battery in response to a charging instruction for the rechargeable battery; obtaining a real-time impedance of the rechargeable battery, and determining an impedance interval in the DCR curve corresponding to the real-time impedance; and determining a current charging strategy for the rechargeable battery according to the impedance interval corresponding to the real-time impedance, and charging the rechargeable battery by using the current charging strategy.

Abstract: A dual-VIO integrated circuit is configurable into either a first configuration in which a VIO power supply voltage has a first value or into a second configuration in which the VIO power supply voltage has a second value. The dual-VIO integrated circuit includes a smart start-up detection circuit that detects whether the integrated circuit is in the first configuration or the second configuration.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An apparatus is disclosed for enhanced reverse isolation and gain using feedback. The apparatus includes an input node, an amplification node, a feedback node, an output circuit, at least one amplifier circuit, and a feedback circuit. The output circuit is connected between the amplification node and the feedback node. The at least one amplifier circuit is connected between the input node and the amplification node. The at least one amplifier circuit includes an input transistor and a cascode stage. The input transistor has a gate node and a drain node, and the gate node is connected to the input node. The cascode stage is connected between the drain node and the amplification node. The feedback circuit includes at least one feedback capacitor that is connected between the feedback node and the input node.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An apparatus including: a plurality of amplifiers having a plurality of output ports, respectively, the plurality of amplifiers configured to amplify radio frequency (RF) signals received from at least one antenna; a plurality of demodulators configured to receive the amplified RF signals at a plurality of input ports, respectively, the plurality of demodulators configured to downconvert the received RF signals; and a plurality of switches configured to couple selected output ports of the plurality of amplifiers to selected input ports of the plurality of demodulators, wherein each switch of the plurality of switches is configured such that at least one of the plurality of output ports of the plurality of amplifiers is selectively coupled to any of multiple input ports of the plurality of input ports of the plurality of demodulators.

Abstract: An apparatus including: a plurality of amplifiers having a plurality of output ports, respectively, the plurality of amplifiers configured to amplify radio frequency (RF) signals received from at least one antenna; a plurality of demodulators configured to receive the amplified RF signals at a plurality of input ports, respectively, the plurality of demodulators configured to downconvert the received RF signals; and a plurality of switches configured to couple selected output ports of the plurality of amplifiers to selected input ports of the plurality of demodulators, wherein each switch of the plurality of switches is configured such that at least one of the plurality of output ports of the plurality of amplifiers is selectively coupled to any of multiple input ports of the plurality of input ports of the plurality of demodulators.

Abstract: A dual stage LNA for use in multiband receivers is disclosed. In an exemplary embodiment, an apparatus includes a plurality of first stage amplifiers having a plurality of first stage output ports, respectively, to output first stage amplified voltage mode signals. The apparatus also includes a plurality of second stage amplifiers having a plurality of second stage input ports, respectively, and second stage output ports to output amplified current mode signals. The apparatus also includes a switch apparatus having input terminals connected to the first stage output ports and output terminals connected to the second stage input ports, the switch apparatus to connect selected second stage input ports to selected first stage output ports.

Abstract: An apparatus for reducing a harmonic response in an electronic circuit is provided. The apparatus includes an RF input configured to provide a first signal operating at a radio frequency. The apparatus includes a local oscillator configured to produce a second signal operating at a local oscillator (LO) frequency. The apparatus includes a switching mixer configured to mix the first and second signals. The apparatus includes a notch filter comprising an inductor and a capacitor connected in parallel. The notch filter is directly coupled to an input of the switching mixer in series. The notch filter is tuned such that its resonant frequency is a harmonic of the LO frequency signal. In an aspect, the apparatus also includes a transformer configured to provide the first signal. In an aspect the apparatus also includes a second notch filter comprising a second inductor and a second capacitor connected in parallel.