Abstract: A Cathode material and a preparation method therefor and use thereof are provided. The cathode material includes a cathode active substrate, and a surface of the cathode active substrate is coated with a carbon coating layer, wherein a surface of the carbon coating layer has an esterophilic group. The invention changes the surface energy of the carbon coating layer by introducing the esterophilic carbonyl to the surface of the carbon coating layer of the cathode active substrate, thereby significantly improving the wettability of the cathode active particles to the electrolyte. Moreover, the bulk structure of the active material is not changed, so the electrochemical performance of the cathode active material is guaranteed. The cathode plate prepared by the invention shows excellent wettability in the electrolyte, and a prepared battery shows low internal resistance, high energy efficiency and other characteristics.

Abstract: Disclosed are a battery charging method, a battery charging device, and a battery charging apparatus. The battery charging method, comprising: determining a direct current resistance (DCR) curve of a rechargeable battery in response to a charging instruction for the rechargeable battery; obtaining a real-time impedance of the rechargeable battery, and determining an impedance interval in the DCR curve corresponding to the real-time impedance; and determining a current charging strategy for the rechargeable battery according to the impedance interval corresponding to the real-time impedance, and charging the rechargeable battery by using the current charging strategy.

Abstract: A method for preparing an energy storage cell is provided, and includes: providing a film layer, where the film layer is one of a positive electrode sheet, a separating film, and a negative electrode sheet, and the film layer has a first edge and a second edge opposite the first edge; performing a dispensing treatment on the film layer to form a plurality of groups of glue dots arranged on a surface of the film layer in a first direction; providing remaining two of the positive electrode sheet, the separating film, and the negative electrode sheet, and stacking the negative electrode sheet, the separating film, and the positive electrode sheet sequentially to form a stacked structure; and performing a winding treatment on the stacked structure from the second edge toward the first edge.

Abstract: A method for determining a remote radio device and a distributed AP are provided. The method includes: A baseband device determines parameters of uplink signals received by N remote radio devices, where N is a natural number greater than 1. The baseband device selects, based on the parameters, at least one remote radio device from the N remote radio devices as a remote radio device in a target set. The baseband device performs decoding based on an uplink signal received by the remote radio device in the target set, or positions a terminal device based on an uplink signal received by the remote radio device in the target set.

Abstract: The present disclosure provides a radio frequency apparatus, an antenna and an electronic device, and belongs to the field of communication technology. The radio frequency apparatus includes first and second dielectric substrates opposite to each other, first and second phase shifting structures between the first and second dielectric substrates; wherein the radio frequency apparatus further includes a first connection electrode and a second connection electrode; the first phase shifting structure and the second phase shifting structure each have a first end and a second end, the first ends of the first phase shifting structure and the second phase shifting structure are electrically connected to each other by the first connection electrode; the second ends of the first phase shifting structure and the second phase shifting structure are electrically connected to each other by the second connection electrode, to form a ring circuit structure.

Abstract: A dual-VIO integrated circuit is configurable into either a first configuration in which a VIO power supply voltage has a first value or into a second configuration in which the VIO power supply voltage has a second value. The dual-VIO integrated circuit includes a smart start-up detection circuit that detects whether the integrated circuit is in the first configuration or the second configuration.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An apparatus is disclosed for enhanced reverse isolation and gain using feedback. The apparatus includes an input node, an amplification node, a feedback node, an output circuit, at least one amplifier circuit, and a feedback circuit. The output circuit is connected between the amplification node and the feedback node. The at least one amplifier circuit is connected between the input node and the amplification node. The at least one amplifier circuit includes an input transistor and a cascode stage. The input transistor has a gate node and a drain node, and the gate node is connected to the input node. The cascode stage is connected between the drain node and the amplification node. The feedback circuit includes at least one feedback capacitor that is connected between the feedback node and the input node.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.

Abstract: An apparatus including: a plurality of amplifiers having a plurality of output ports, respectively, the plurality of amplifiers configured to amplify radio frequency (RF) signals received from at least one antenna; a plurality of demodulators configured to receive the amplified RF signals at a plurality of input ports, respectively, the plurality of demodulators configured to downconvert the received RF signals; and a plurality of switches configured to couple selected output ports of the plurality of amplifiers to selected input ports of the plurality of demodulators, wherein each switch of the plurality of switches is configured such that at least one of the plurality of output ports of the plurality of amplifiers is selectively coupled to any of multiple input ports of the plurality of input ports of the plurality of demodulators.

Abstract: An apparatus including: a plurality of amplifiers having a plurality of output ports, respectively, the plurality of amplifiers configured to amplify radio frequency (RF) signals received from at least one antenna; a plurality of demodulators configured to receive the amplified RF signals at a plurality of input ports, respectively, the plurality of demodulators configured to downconvert the received RF signals; and a plurality of switches configured to couple selected output ports of the plurality of amplifiers to selected input ports of the plurality of demodulators, wherein each switch of the plurality of switches is configured such that at least one of the plurality of output ports of the plurality of amplifiers is selectively coupled to any of multiple input ports of the plurality of input ports of the plurality of demodulators.

Abstract: A dual stage LNA for use in multiband receivers is disclosed. In an exemplary embodiment, an apparatus includes a plurality of first stage amplifiers having a plurality of first stage output ports, respectively, to output first stage amplified voltage mode signals. The apparatus also includes a plurality of second stage amplifiers having a plurality of second stage input ports, respectively, and second stage output ports to output amplified current mode signals. The apparatus also includes a switch apparatus having input terminals connected to the first stage output ports and output terminals connected to the second stage input ports, the switch apparatus to connect selected second stage input ports to selected first stage output ports.

Abstract: An apparatus for reducing a harmonic response in an electronic circuit is provided. The apparatus includes an RF input configured to provide a first signal operating at a radio frequency. The apparatus includes a local oscillator configured to produce a second signal operating at a local oscillator (LO) frequency. The apparatus includes a switching mixer configured to mix the first and second signals. The apparatus includes a notch filter comprising an inductor and a capacitor connected in parallel. The notch filter is directly coupled to an input of the switching mixer in series. The notch filter is tuned such that its resonant frequency is a harmonic of the LO frequency signal. In an aspect, the apparatus also includes a transformer configured to provide the first signal. In an aspect the apparatus also includes a second notch filter comprising a second inductor and a second capacitor connected in parallel.

Abstract: An apparatus for reducing a harmonic response in an electronic circuit is provided. The apparatus includes an RF input configured to provide a first signal operating at a radio frequency. The apparatus includes a local oscillator configured to produce a second signal operating at a local oscillator (LO) frequency. The apparatus includes a switching mixer configured to mix the first and second signals. The apparatus includes a notch filter comprising an inductor and a capacitor connected in parallel. The notch filter is directly coupled to an input of the switching mixer in series. The notch filter is tuned such that its resonant frequency is a harmonic of the LO frequency signal. In an aspect, the apparatus also includes a transformer configured to provide the first signal. In an aspect the apparatus also includes a second notch filter comprising a second inductor and a second capacitor connected in parallel.

Abstract: A dual stage LNA for use in multiband receivers is disclosed. In an exemplary embodiment, an apparatus includes a plurality of first stage amplifiers having a plurality of first stage output ports, respectively, to output first stage amplified voltage mode signals. The apparatus also includes a plurality of second stage amplifiers having a plurality of second stage input ports, respectively, and second stage output ports to output amplified current mode signals. The apparatus also includes a switch apparatus having input terminals connected to the first stage output ports and output terminals connected to the second stage input ports, the switch apparatus to connect selected second stage input ports to selected first stage output ports.

Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.