Patents by Inventor Zixiong William Wang

Zixiong William Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe bridges
    Patent number: 9143346
    Abstract: A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.
    Type: Grant
    Filed: October 31, 2010
    Date of Patent: September 22, 2015
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Mohammad Shahanshah Akhter, Zixiong William Wang, David Clifton Bond, Gregory Edward Lund
  • Method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe bridges
    Patent number: 8949501
    Abstract: A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.
    Type: Grant
    Filed: October 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Integrated Device Technology, Inc.
    Inventors: Mohammad Shahanshah Akhter, Zixiong William Wang, David Clifton Bond, Gregory Edward Lund
  • Method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe bridges
    Patent number: 8730983
    Abstract: A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.
    Type: Grant
    Filed: October 31, 2010
    Date of Patent: May 20, 2014
    Assignee: Integrated Device Technology, Inc.
    Inventors: Mohammad Shahanshah Akhter, Zixiong William Wang, David Clifton Bond, Gregory Edward Lund