Abstract: An integrateable circuit is disclosed which allows selection between pre-defined and user-defined characteristics. The circuit utilizes a single input terminal for both selection and definition by a user. In a preferred embodiment, a comparator senses whether a user-supplied voltage at this input terminal is at a logic low level or not. If the voltage at this input terminal is at a logic level low, an internal voltage proportional to a pre-defined characteristic is enabled. If the voltage at this input terminal is not at a logic low level, the internal voltage proportional to the pre-defined characteristic is disconnected and a characteristic defined by the user, its value proportional to the user-supplied voltage present at the input terminal, is connected and activated.

Abstract: An integrateable circuit is disclosed which allows selection between pre-defined and user-defined characteristics. The circuit utilizes a single input terminal for both selection and definition by a user. In a preferred embodiment, a comparator senses whether a user-supplied voltage at this input terminal is at a logic low level or not. It the voltage at this input terminal is at a logic level low, an internal voltage proportional to a pre-defined characteristic is enabled. If the voltage at this input terminal is not at a logic low level, the internal voltage proportional to the pre-defined characteristic is disconnected and a characteristic defined by the user, its value proportional to the user-supplied voltage present at the input terminal, is connected and activated.

Abstract: An improved analog to digital converter in which an approximate digital representation is provided by a parallel analog to digital converter and the conversion is completed by a successive approximation analog to digital converter.

Abstract: A high accuracy monolithic digital to analog converter (DAC) which employs an EPROM controlled correction DAC to correct for errors in the output of a primary DAC. The correction DAC empolys a non-binary bit weighting which permits the use of low accuracy components in the fabrication of the correction DAC. The output of the primary DAC is skewed so that the required correction is always in a single direction, thereby eliminating the need for a constant offset generator. Resistors necessary for bipolar operation are included on the chip, thereby eliminating the need for connection of any external resistors to achieve such operation.