Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: This application discloses a voltage analysis tool to perform a static power aware analysis on a circuit design without having to simulate the circuit design. The voltage analysis tool can determine a set of components in the circuit design corresponds to a design pattern representing a voltage-transition device, and set an output voltage for the set of components based, at least in part, on characteristics of the voltage-transition device. The voltage analysis tool can propagate the output voltage to other portions of the circuit design, and determine whether the portions of the circuit design receiving the output voltage have a rule violation.

Abstract: This application discloses a voltage analysis tool to perform a static power aware analysis on a circuit design without having to simulate the circuit design. The voltage analysis tool can determine a set of components in the circuit design corresponds to a design pattern representing a voltage-transition device, and set an output voltage for the set of components based, at least in part, on characteristics of the voltage-transition device. The voltage analysis tool can propagate the output voltage to other portions of the circuit design, and determine whether the portions of the circuit design receiving the output voltage have a rule violation.

Abstract: Techniques for analysis of an electrical circuit design are described, which techniques employ two phases: an initialization phase, and a check phase. During the initialization phase, a circuit design is examined to determine the predicted operating characteristics at various nodes within the design. If the design is hierarchically arranged, then the design is analyzed in a way that preserves its hierarchy. During the check phase, various implementations of the invention will check the determined operating characteristic values to see if they indicate that one or more design rules have been violated. A user may specify or “program” aspects of the analysis, both for the initialization phase and the check phase.

Abstract: Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria.

Abstract: Electrical rule checking techniques for analyzing integrated circuit design data to identify specified circuit element configurations. Both tools and methods implementing these techniques may be employed to identify circuit element configurations using both logical and physical layout information for the design data. A set of commands are provided that will allow a user to program a programmable electrical rule check tool to identify a wide variety of circuit element configurations, using both logical and physical layout data, as desired by the user.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: A virtual tester, for testing a device logic simulator, includes multiple virtual instruments that generate stimulus messages for delivery to the device logic simulator and for receiving response messages generated by the device logic simulator. Each virtual instrument models a corresponding hardware test instrument and comprises a concrete instrument model that behaves in a manner corresponding to the corresponding hardware test instrument and also comprises an abstract interface that is independent of the behavior of the corresponding hardware test instrument. At least one virtual instrument generates sync messages for coordinating operation of the virtual instruments.

Abstract: A GUI-based API for a test system provides a user-friendly interface for generating API function calls in one of several different programming languages, as selected by the user. The GUI-based API prompts the user to select from a list of valid API functions, which are generated based on the test system configuration. The values for the selected API function parameters are then specified by selecting from a valid list of choices or by entering an arbitrary value. The valid list of choices presented to the user for selection is generated based on the test system configuration and on the prior parameter values specified by the user. For API functions including parameters that have a main parameter and optional parameters, input interfaces for specifying the values for the optional parameters are also presented to the user. Every parameter of the selected API function is processed, so that when the last parameter is processed, an appropriate end of function signature is automatically inserted.

Abstract: A method of verifying test data for testing an integrated circuit device having multiple device time domains includes selecting a virtual tester time domain and, if the cycle duration of the virtual tester time domain is equal to the cycle duration of one of the multiple device time domains, translating the test data for each device time domain other than that one time domain to the virtual tester time domain and otherwise translating the test data for each device time domain to the virtual tester time domain. The translated test data is then applied to a device logic simulator that simulates integrated circuit device.