Abstract: A display substrate includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit includes an initial signal line, a reset signal line, a scan signal line and multiple transistors. Multiple transistors include a drive transistor, a data writing transistor, a first reset transistor and a second reset transistor. The first reset transistor resets a gate of the drive transistor under control of the reset signal line. The display substrate further comprises dummy pixel rows among the plurality of sub-pixels, at least one row of the plurality of sub-pixels is arranged adjacent to a dummy pixel row, the dummy pixel row comprises a plurality of dummy sub-pixels, a dummy sub-pixel comprises a dummy pixel drive circuit.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a first region and a second region surrounded by the first region. The display substrate includes first signal lines and second signal lines extending along different directions. The first signal line includes a first sub-signal line and a second sub-signal line located on both sides of the second region and are electrically connected through a first connection line and a second connection line extending in different directions; the second signal line includes a third sub-signal line and a fourth sub-signal line located on both sides of the second region and are electrically connected through a third connection line overlapped with the second connection line and a fourth connection line extending in different directions; and at least one first connection line is farther from the second region than at least one third connection line.

Abstract: A display substrate, a display panel and a display device are provided. The display substrate includes: sub-pixels; a first initialization voltage signal line; a first electrode disposed on the base substrate; a pixel defining layer disposed on a side of the first electrode layer away from the base substrate. At least one sub-pixel includes a pixel opening located in the pixel defining layer. The first initialization voltage signal line includes a first sub-line with a main body extending in a first direction and a second sub-line with a main body extending in a second direction. An orthographic projection of one second sub-line on the base substrate is located on a first side of a midpoint of a pixel opening of one first sub-pixel, and an orthographic projection of another second sub-line on the base substrate is located on a second side of a midpoint of a pixel opening of the other first sub-pixel.

Abstract: Provided are a display substrate and a display device. The display substrate includes: a base substrate; a driving circuit layer; a pixel defining layer defining pixel openings for pixels; at least part of a light emitting unit layer is provided in the pixel openings, the light emitting unit layer includes an anode layer near the driving circuit layer, the anode layer includes a first anode region partially located in the pixel openings and a second anode region located outside the pixel openings, and the first anode region and the second anode region of a same pixel are electrically connected; a black matrix layer defining black matrix openings; and a color filter layer. Overlapping regions are formed by orthographic projections of the driving circuit layer and the first anode region on the base substrate, and wires of the driving circuit layer in at least part of the overlapping regions are axisymmetric.

Abstract: A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: Disclosed are a display substrate and a display device. The display substrate includes: a base substrate, the base substrate including a display region and a bezel region on at least one side of the display region; a first electrode on the base substrate, where the first electrode extends from the display region to the bezel region; a first power bus between the layer where the first electrode is located and the base substrate, where the first power bus is in the bezel region and is electrically connected with the first electrode; and a first power line between the layer where the first electrode is located and the base substrate, where the first power line is in the display region, where the first power line is in the display region, is of a mesh structure, and is electrically connected with the first power bus.

Abstract: A driving circuit, a driving method, a driving module and a display device are provided. The driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a third control node control circuit. The third control node control circuit is electrically connected to the first node and the third control node respectively, and is configured to control the potential of the third control node according to the potential of the first node.

Abstract: An array substrate is provided. The array substrate includes a plurality of first subpixels in a first region and a plurality of second subpixels in a second region. The plurality of first subpixels include a plurality of first pixel driving circuits. The plurality of second subpixels include a plurality of second pixel driving circuits. A respective first pixel driving circuit of the plurality of first pixel driving circuits includes a smaller number of transistors than a respective second pixel driving circuit of the plurality of second pixel driving circuits. The first region has a light transmittance higher than the second region, and a subpixel density same as the second region.

Abstract: A method for treating AR+ breast cancer in a subject comprising administering to the subject an AR agonist (e.g., SARMs such as RAD140), or in combination with one or more therapeutic agents selected from the group consisting of cdk4/6 inhibitors, m-TOR inhibitors, PI3k inhibitors, PARP inhibitors, BCL-2 inhibitors, and MCL-1 inhibitors.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: A display panel includes a pixel drive circuit for driving a light emitting unit. The pixel drive circuit is connected to the first electrode of the light emitting unit, and the display panel further includes: a base substrate, a first power line, a second power line, and a common electrode layer. The first power line and the second power line are located a the display area of the display panel, the orthographic projection of the first power line on the base substrate is extended along the first direction, the orthographic projection of the second power line on the base substrate is extended along the second direction, and the second direction is intersected with the first direction, at least a part of the second power line is connected to at least a part of the first power line through a via hole.

Abstract: A display panel includes a light-emitting unit and a pixel driving circuit connected to the first electrode of the light-emitting unit. The display panel further includes: a substrate, a first power line, a second power line, and a common electrode layer. The display area includes at least one fan-out area and a normal display area, and the part of the second power line located in the normal display area is connected to the first power line. The first power line includes a first sub-power line segment located in the fan-out area; the second power line includes a second sub-power line segment located in the fan-out area; the first sub-power line segment and the second sub-power line segment are connected; the common electrode layer is used to form the second electrode of the light-emitting unit and connects the first power line and the second power line.

Abstract: A display panel includes: a light emitting unit; a base substrate, including a light transmitting area; a light shielding layer, located on a side of the base substrate and configured with a light shielding function; a pixel defining layer, located on a side of the light shielding layer away from the base substrate, wherein a pixel opening is formed on the pixel defining layer, and the light emitting unit is formed in the pixel opening; and multiple functional layers, located between the base substrate and the pixel defining layer, and orthographic projections, on the base substrate, of light shielding structures of the multiple functional layers are located outside the light transmitting area; wherein a first opening is formed on the light shielding layer, and an orthographic projection of the first opening on the base substrate is located in the light transmitting area.

Abstract: A driving circuit includes a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; N is a positive integer; the first gating circuit controls to write the gating input signal into the first first node under the control of the gating control signal; the first output circuit controls to connect the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and controls to connect the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the first third control node; the first third control node and the first second control node are different nodes.

Abstract: A pixel circuit includes a data writing sub-circuit, a driving sub-circuit, and one or more potential maintenance sub-circuits. The data writing sub-circuit is coupled to at least a first voltage signal terminal, a data signal terminal, a first scan signal terminal and a first node, and writes a data signal provided by the data signal terminal into the first node under control of at least a first scan signal provided by the first scan signal terminal. The driving sub-circuit is coupled to the first node, a second node and a third node, and creates a path between the second node and the third node under control of a potential at the first node. A potential maintenance sub-circuit is coupled to a circuit node and a reference signal terminal, and maintains a potential at the circuit node through a reference signal provided by the reference signal terminal.

Abstract: A pixel circuit, a driving method therefor, a display substrate and a display apparatus, the pixel circuit includes a node control sub-circuit, a storage sub-circuit, a driving sub-circuit and a light emitting control sub-circuit; the storage sub-circuit is electrically connected to a second node and a first power supply line respectively, and is configured to charge the second node when a first scanning signal line is an effective level signal.

Abstract: The present disclosure relates to a display panel with a display area, a first non-display area and a second non-display area are correspondingly disposed on opposite sides of the display area in a first direction, and a binding area is disposed on a side of the second non-display area away from the display area. The display panel includes: a first wire, disposed in the display area and extending along the first direction, wherein the first wire is electrically coupled to a plurality of pixels arranged along the first direction; a second wire, extending along the first direction and extending from the display area to the first non-display area, the second non-display area and the binding area; a connection wire, disposed in the first non-display area and coupled between the first wire and the second wire; and a binding pin, disposed in the binding area and coupled to the second wire.

Abstract: Provided are a display substrate, a driving method thereof, and a display apparatus. The display substrate includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit includes an initial signal line (INIT), a reset signal line (Reset) and multiple transistors, the initial signal line includes a first branch (INIT-1). Multiple transistors include a drive transistor, a first reset transistor and a second reset transistor, the drive transistor provides a drive current to the light emitting device, the first reset transistor resets a gate of the drive transistor through the INIT-1 under control of the reset signal line. The second reset transistor resets a first terminal of the light emitting device through the INIT-1 under control of the reset signal line. The first reset transistor and the second reset transistor in a same sub-pixel are controlled by a same reset signal line.

Abstract: A displaying base board includes an active area and a peripheral region, the peripheral region includes at least a first blocking part and a second blocking part; the peripheral region further includes a first power-supply signal line, and an orthographic projection of the first power-supply signal line on a substrate of the displaying base board has an overlapping part with individually an orthographic projection of the first blocking part on the substrate and an orthographic projection of the second blocking part on the substrate; and the first power-supply signal line is provided with a plurality of openings, and a region enclosed by orthographic projections on the substrate of outer contours of some of the openings falls within a region of the orthographic projection on the substrate of at least one of the first blocking part and the second blocking part.