Abstract: An insulated gate field effect transistor (IGFET) structure (10) includes a source region (14) and a drain region (16) formed in an impurity well (13). A channel region (18) separates the source region (14) from the drain region (16). In one embodiment, a unilateral extension region (17) is formed adjacent the source region (14) only and extends into the channel region (18). The unilateral extension region (17) has a peak dopant concentration at a depth (23) and a lateral distance (24) to provide punchthrough resistance. The IGFET structure (10) is suitable for low (i.e., 0.2-0.3 volts) to medium (0.5-0.6 volts) threshold voltage reduced channel length applications.

Abstract: A non-volatile memory unit (10) includes a memory cell (13) and a reference cell (20). The memory cell (13) includes a ferroelectric memory capacitor (14), which is polarized to store a logic data. The reference cell (20) includes two ferroelectric reference capacitors (25, 26) which are in polarization states (51, 52) complementary to each other. The capacitance of the reference capacitor (25, 26) tracks the capacitance of the memory capacitor (14). When reading data from the memory unit (10), an extraction signal (19A) generates a data voltage depending on the data stored in the memory unit (10), and a reference extraction signal (39A) generates a reference voltage through the reference capacitors (25, 26). A sense amplifier (42) senses the data voltage and the reference voltage, thereby reading data from the memory unit (10).