Abstract: A storage management apparatus, a storage management method, a processor, and a computer system are disclosed. The storage management apparatus includes a translation look-aside buffer, configured to store a plurality of cache entries, wherein the plurality of cache entries comprises a first plurality of level 1 cache entries and a second plurality of level 2 cache entries, wherein the first plurality of level 1 cache entries is less than or equal to the second plurality of level 2 cache entries, and each of the first plurality of level 1 cache entries is different from each of the second plurality of level 2 cache entries; and an address translation unit adapted to translate, based on at least one of the first plurality of level 1 cache entries and the second plurality of level 2 cache entries, a virtual address specified by a translation request into a corresponding translated address.

Abstract: A storage management apparatus, a storage management method, a processor, and a computer system are disclosed. The storage management apparatus includes: at least one translation look-aside buffer, configured to store a plurality of cache entries, where the plurality of cache entries include a plurality of level 1 cache entries and a plurality of level 2 cache entries; and an address translation unit, coupled to the at least one translation look-aside buffer, and adapted to translate, based on one of the plurality of level 1 cache entries, a virtual address specified by a translation request into a corresponding translated address, or when the translation request does not hit any one of the plurality of level 1 cache entries, translate, based on one of the plurality of level 2 cache entries, a virtual address specified by the translation request into a corresponding translated address.

Abstract: The present invention discloses a memory management unit, an address translation method, and a processor. The memory management unit includes: a translation lookaside buffer adapted to store a plurality of translation entries, where each translation entry includes a size flag bit, a virtual address tag, and a physical address tag, the virtual address tag represents a virtual page, the physical address tag represents a physical page corresponding to the virtual pane, and the size flag bit represents a page size of the virtual page; and a translation processing unit adapted to look up a translation entry whose virtual address tag matches a to-be-translated virtual address in the plurality of translation entries based on the page size represented by the size flag bit of the translation entry, and translate the virtual address into a physical address based on the matching translation entry.

Abstract: The present invention discloses a memory management unit, an address translation method, and a processor.

Abstract: A storage management apparatus, a storage management method, a processor, and a computer system are disclosed. The storage management apparatus includes: at least one translation look-aside buffer, configured to store a plurality of cache entries, where the plurality of cache entries include a plurality of level 1 cache entries and a plurality of level 2 cache entries; and an address translation unit, coupled to the at least one translation look-aside buffer, and adapted to translate, based on one of the plurality of level 1 cache entries, a virtual address specified by a translation request into a corresponding translated address, or when the translation request does not hit any one of the plurality of level 1 cache entries, translate, based on one of the plurality of level 2 cache entries, a virtual address specified by the translation request into a corresponding translated address.

Abstract: A storage management apparatus, a storage management method, a processor, and a computer system are disclosed. The storage management apparatus includes: a translation look-aside buffer configured to store a plurality of cache entries; an address translation unit configured to translate a virtual address specified by a translation request to a corresponding translation address based on one of the plurality of cache entries; and a control unit coupled to at least one translation look-aside buffer and configured to expand an address range mapped to the selected cache entry. According to embodiments of this disclosure, a translatable address range of the translation look-aside buffer can be expanded, a hit rate of the translation look-aside buffer can be increased, and an execution time of address translation can be reduced, thereby improving performance of the processor and the system.