Patents by Inventor Ziyin LIN

Ziyin LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250112161
    Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Minglu Liu, Seyyed Yahya Mousavi, Yingying Zhang, Gang Duan, Andrey Gunawan, Yosuke Kanaoka, Yiqun Bai, Ziyin Lin, Bohan Shan, Dingying Xu, Srinivas Pietambaram, Hong Seung Yeon
  • Publication number: 20250112085
    Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Ziyin Lin, Haobo Chen, Yiqun Bai, Kyle Arrington, Jose Waimin, Ryan Carrazzone, Hongxia Feng, Dingying Xu, Srinivas Pietambaram, Minglu Liu, Seyyed Yahya Mousavi, Xinyu Li, Gang Duan, Wei Li, Bin Mu, Mohit Gupta, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo, Ashay Dani
  • Publication number: 20250112136
    Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
  • Publication number: 20250110295
    Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Saikumar Jayaraman, Yiqun Bai, Fan Fan, Dingying Xu
  • Publication number: 20250112164
    Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Bohan SHAN, Onur OZKAN, Ryan CARRAZZONE, Rui ZHANG, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Venkata Rajesh SARANAM, Shripad GOKHALE, Kartik SRINIVASAN, Edvin CETEGEN, Mine KAYA, Nicholas S. HAEHN, Deniz TURAN
  • Publication number: 20250106983
    Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Inventors: Bohan SHAN, Kyle ARRINGTON, Dingying David XU, Ziyin LIN, Timothy GOSSELIN, Elah BOZORG-GRAYELI, Aravindha ANTONISWAMY, Wei LI, Haobo CHEN, Yiqun BAI, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Ashay DANI
  • Publication number: 20250102744
    Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Kumar Abhishek Singh, Peter A. Williams, Ziyin Lin, Fan Fan, Yang Wu, Saikumar Jayaraman, Baris Bicen, Darren Vance, Anurag Tripathi, Divya Pratap, Stephanie J. Arouh
  • Publication number: 20250105074
    Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Wei Wei, Jose Fernando Waimin Almendares, Ryan Joseph Carrazzone, Kyle Jordan Arrington, Ziyin Lin, Dingying Xu, Hongxia Feng, Yiqun Bai, Hiroki Tanaka, Brandon Christian Marin, Jeremy Ecton, Benjamin Taylor Duong, Gang Duan, Srinivas Venkata Ramanuja Pietambaram, Rui Zhang, Mohit Gupta
  • Publication number: 20250079278
    Abstract: In one embodiment, an apparatus comprises a substrate with conductive contacts on a first side of the substrate and a housing coupled to the first side of the substrate. The housing defines a set of holes around the conductive contacts. The apparatus further includes Gallium-based liquid metal in each hole, with the liquid metal being in contact with the conductive contact of the hole. The apparatus further includes a passivation layer on a surface of the liquid metal in each hole, the passivation layer being on an opposite end of the hole from the conductive contact in the hole.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Applicant: Intel Corporation
    Inventors: Karumbu Nathan Meyyappan, Pooya Tadayon, Ziyin Lin, Gregory A. Stone
  • Publication number: 20240402445
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Inventors: Bassam ZIADEH, Jingyi HUANG, Yiqun BAI, Ziyin LIN, Vipul MEHTA, Joseph VAN NAUSDLE
  • Publication number: 20240388018
    Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a first surface and a second surface opposite from the first surface. In an embodiment, pads are on the first surface of the package substrate, where the pads have a first width. In an embodiment, a layer is on the first surface of the package substrate, where the layer comprises wells through the layer, and where the wells have a second width that is wider than the first width. In an embodiment, a liquid metal is in the wells and in contact with the pads.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: Karumbu MEYYAPPAN, Gregorio R. MURTAGIAN, Ziyin LIN
  • Publication number: 20240363520
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a substrate with a layer on the substrate. In an embodiment, the layer comprises a plurality of wells. In an embodiment, a liquid metal is in the plurality of wells. In an embodiment, a cap is on the layer to seal the plurality of wells, where the cap comprises a polymer, and fibers within the polymer.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Inventors: Ziyin LIN, Boer LIU, Dingying David XU, Karumbu MEYYAPPAN
  • Patent number: 12130482
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Bassam Ziadeh, Jingyi Huang, Yiqun Bai, Ziyin Lin, Vipul Mehta, Joseph Van Nausdle
  • Publication number: 20240332125
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a first layer and a second layer over the first layer. In an embodiment, the second layer comprises a dielectric material including sulfur. In an embodiment, fillers are within the second layer. In an embodiment, the fillers have a volume fraction that is less than approximately 0.2.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: Kyle ARRINGTON, Clay ARRINGTON, Bohan SHAN, Haobo CHEN, Srinivas V. PIETAMBARAM, Gang DUAN, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying XU, Bai NIE
  • Publication number: 20240312865
    Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Kyle Arrington, Bohan Shan, Haobo Chen, Bai Nie, Srinivas Pietambaram, Gang Duan, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
  • Patent number: 12068222
    Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
  • Publication number: 20240270929
    Abstract: Capillary underfill formulations that may include fillers. The fillers may include carbon nanotubes, such as surface functionalized carbon nanotubes. Methods for forming capillary underfill materials that may have improved fracture toughness, reduced crack propagation, and a reduced likelihood of delamination. The surface functionalized carbon nanotubes may include amine functionalized carbon nanotubes. Containers, such as syringes, that may have a reservoir in which a capillary underfill formulation is disposed.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 15, 2024
    Inventors: Clay Arrington, Kyle Arrington, Ziyin Lin, Jose Waimin, Dingying Xu
  • Publication number: 20240219656
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20240219660
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Yiqun Bai, Dingying Xu, Eric J.M. Moret, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Bin Mu
  • Publication number: 20240219654
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram