Patents by Inventor Ziyin LIN
Ziyin LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240222243Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
-
Publication number: 20240222304Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Bohan Shan, Jiaqi Wu, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
-
Publication number: 20240219660Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Hongxia Feng, Haobo Chen, Yiqun Bai, Dingying Xu, Eric J.M. Moret, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Bin Mu
-
Publication number: 20240219656Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
-
Publication number: 20240219655Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Haobo Chen, Bohan Shan, Bai Nie, Brandon C. Marin, Dingying Xu, Gang Duan, Hongxia Feng, Jeremy D. Ecton, Kristof Darmawikarta, Kyle Jordan Arrington, Srinivas Venkata Ramanuja Pietambaram, Xiaoying Guo, Yiqun Bai, Ziyin Lin
-
Publication number: 20240222136Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ashay A. Dani, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Wei Wei, Ziyin Lin
-
Publication number: 20240222257Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Ziyin Lin, Rahul N. Manepalli, Brandon C. Marin, Jeremy D. Ecton
-
Publication number: 20240222301Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Dingying Xu, Sairam Agraharam, Ashay Dani, Eric J. M. Moret, Tarek Ibrahim
-
Publication number: 20240219654Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
-
Publication number: 20240222238Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Bai Nie, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
-
Publication number: 20240222259Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Haobo Chen, Bohan Shan, Xiyu Hu, Rhonda Jack, Catherine Mau, Hongxia Feng, Xiao Liu, Wei Wei, Srinivas Pietambaram, Gang Duan, Xiaoying Guo, Dingying Xu, Kyle Arrington, Ziyin Lin, Hiroki Tanaka, Leonel Arana
-
Publication number: 20240222210Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
-
Publication number: 20240222345Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Pietambaram, Gang Duan, Kyle Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
-
Publication number: 20240219659Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
-
Publication number: 20240213164Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and an opening in the package substrate. In an embodiment, a plurality of first pads are provided at a bottom of the opening, and a bridge die is in the opening. In an embodiment, the bridge die comprises a plurality of second pads that are coupled to the first pads by solder. In an embodiment, a non-conductive film (NCF) is around the solder between the first pads and the second pads.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Inventors: Minglu LIU, Gang DUAN, Liang HE, Ziyin LIN, Elizabeth NOFEN, Yiqun BAI, Jonathan ATKINS, Jesus S. NIETO PESCADOR, Srinivas V. PIETAMBARAM, Kristof DARMAWIKARTA
-
Publication number: 20240215269Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington
-
Publication number: 20240213116Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Inventors: Kyle Arrington, Bohan Shan, Haobo Chen, Ziyin Lin, Hongxia Feng, Yiqun Bai, Dingying Xu, Xiaoying Guo, Bai Nie, Srinivas Pietambaram, Gang Duan
-
Publication number: 20240213169Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
-
Publication number: 20240213170Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
-
Publication number: 20240186228Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus. The metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.Type: ApplicationFiled: December 2, 2022Publication date: June 6, 2024Applicant: Intel CorporationInventors: Haobo Chen, Bohan Shan, Kyle J. Arrington, Yiqun Bai, Kristof Darmawikarta, Gang Duan, Jeremy D. Ecton, Hongxia Feng, Xiaoying Guo, Ziyin Lin, Brandon Christian Marin, Bai Nie, Srinivas V. Pietambaram, Dingying Xu