Abstract: In embodiments herein, circuit components are embedded within a core layer of a substrate. The circuit components are vertically oriented within a cavity or hole of the core layer of the substrate, e.g., with conductive contacts on an edge of the component that is substantially orthogonal to a plane of the core layer. The edge that is substantially orthogonal to a plane of the core layer may be the longest edge of the component.

Abstract: Methods for fabricating glass cores with conductive vias (e.g., TGVs), as well as related devices, are disclosed. Methods described herein are based on fabricating pillars of conductive materials (e.g., metals or metal alloys) on a temporary support, inserting the pillars into corresponding via openings in a glass core, and at least partially filling the remaining space in the openings with a filler material.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to embed a semiconductor device in a glass core. An example apparatus comprises a package substrate comprising a glass core having a cavity in an outer surface of the glass core, the outer surface defining a first plane, and a semiconductor die attached to a surface of the cavity, the semiconductor die having contact pads on a surface of the semiconductor die, the contact pads arranged in a second plane, the second plane substantially coplanar with the first plane.

Abstract: Embodiments disclosed herein include passive electrical components with thickness modifications. In an embodiment, such an apparatus may comprise a first substrate with a first material composition, where the first substrate comprises a passive electrical device. In an embodiment, a second substrate is coupled to the first substrate, where the second substrate has a second material composition. In an embodiment, a layer is over a surface of the second substrate opposite from the first substrate, and the layer is electrically insulating.

Abstract: Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.

Abstract: Embodiments disclosed herein include an apparatus with a component embedded in a core. Apparatuses disclosed herein may comprise a first component with a first surface and a second surface opposite from the first surface, where a pad is provided on the first surface. In an embodiment, a layer is over the second surface of the first component, and a second component is over the layer. In an embodiment, the second component comprises a hole that passes through at least a partial thickness of the second component.

Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. A spacer may be included between the power components. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Abstract: Pedestals for semiconductors embedded in package substrates and related methods are disclosed. An example package substrate for an integrated circuit package disclosed herein includes core having a first surface, a second surface, and a cavity formed in the first surface, a semiconductor component disposed in the cavity, and a pedestal disposed in the cavity, the pedestal having a third surface coupled to the semiconductor component, and a fourth surface adjacent to the first surface, the pedestal dimensioned such that a first thickness of the pedestal and semiconductor is substantially equal to a second thickness of the core.

Abstract: Technologies for connected components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Abstract: Embodiments disclosed herein include an apparatus that comprises a first substrate and a second substrate over the first substrate. In an embodiment, an array of interconnects is provided between the first substrate and the second substrate. The array of interconnects comprises a first interconnect with a first material composition, and a second interconnect with a second material composition that is different than the first material composition.

Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer bonded with a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and wherein the first circuit component comprises a deep trench capacitor, and one or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface. Other embodiments are also disclosed and claimed.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a material and conductive pathways through the material, wherein the material includes an organic dielectric material; and a microelectronic component having a first surface and an opposing second surface, wherein the first surface of the microelectronic component is electrically coupled to the conductive pathways in the material by interconnects, wherein the interconnects include solder and are surrounded by a capillary underfill material, and wherein the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.

Abstract: Systems, apparatus, articles of manufacture, and methods to embed semiconductor devices in cores of package substrates are disclosed. An example package substrate includes a core having a first surface and a second surface. The core includes a cavity extending between the first and second surfaces. The example package substrate further includes a semiconductor die within the cavity; a pedestal within the cavity; and an adhesive within the cavity. The adhesive surrounds the semiconductor die and the pedestal. A material of the pedestal different from a material of the adhesive.

Abstract: Various techniques for alleviating crack formation and propagation in glass cores of microelectronic assemblies, and related devices and methods, are disclosed. The techniques are based on including fillers into glass cores and/or in layers provided on top and/or bottom of glass cores. The fillers have at least one characteristic indicative of material's resistance to breaking under stress being higher than that of glass, which may provide reinforcement and/or increase stiffness of glass, thereby strengthening glass cores. Examples of such characteristics include material strength, fracture toughness, or elastic modulus.

Abstract: Embodiments disclosed herein include bridge structures for package substrates. In an embodiment, a package substrate comprises a substrate that is a dielectric material. In an embodiment, a cavity is formed into the substrate. A first pad is on a bottom surface of the cavity, and a die is at least partially in the cavity. In an embodiment, a via passes through at least a portion of a thickness of the die, and a second pad is on the die. In an embodiment, the second pad directly contacts the first pad, and the first pad is the only electrically conductive structure between the via and the second pad.

Abstract: Various techniques for alleviating (e.g., mitigating or reducing) stresses between glass core materials and electrically conductive materials deposited in through-glass vias (TGVs) and related devices and methods are disclosed. In one aspect, a microelectronic assembly includes a glass core having a first face and a second face opposite the first face, and a TGV extending through the glass core between the first face and the second face, wherein the TGV includes a conductive material and a buffer layer between the conductive material and the glass core, wherein a CTE of the buffer layer is smaller than a CTE of the conductive material.

Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.

Abstract: Embodiments disclosed herein include an interconnect structure. In an embodiment, the interconnect structure is an apparatus that comprises a substrate with a well through a thickness of the substrate. In an embodiment, the substrate comprises a polymer foam. In an embodiment, a liquid metal is in the opening, and the liquid metal comprises voids.

Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.