Patents by Inventor Ziyin LIN

Ziyin LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153837
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 9, 2024
    Inventors: Ziyin LIN, Vipul MEHTA, Jonas CROISSANT, Jigneshkumar PATEL, Dingying XU, Gang DUAN, Aditya Sumanth YERRAMILLI, Suriyakala RAMALINGAM, Xavier BRUN
  • Publication number: 20240112971
    Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
  • Publication number: 20240074046
    Abstract: Technologies for integrated circuit components with liquid metal interconnects are disclosed. In the illustrative embodiment, a bed of nails socket can mate with an integrated circuit component with liquid metal interconnects. The nails pierce a foam cap layer that seals the liquid metal interconnects, electrically coupling the nails to the liquid metal interconnects. A fabric layer adjacent to the foam cap layer helps secure the foam cap layer, preventing small pieces of the foam cap layer that may be dislodged during repeated insertion into a bed of nails socket from becoming separated from the foam cap layer. The fabric layer can provide additional benefits, such as removing more of the liquid metal from the nails when the integrated circuit component is removed from the bed of nails socket.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Karumbu Nathan Meyyappan, Dingying Xu
  • Publication number: 20240071848
    Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Bohan SHAN, Haobo CHEN, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Bai NIE, Gang DUAN, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying David XU, Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD
  • Publication number: 20230317668
    Abstract: Embodiments herein relate to systems, apparatuses, or processes that include barriers, which may be referred to as flow stops, to modulate, or control, the speed of flow of an underfill between the substrate and another object on the substrate, for example one or more dies coupled with the substrate. Moderating the speed of flow of the underfill reduces the number of voids in the underfill after curing. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Ziyin LIN, Wei LI, Jingyi HUANG, Hsin-Yu LI
  • Patent number: 11776821
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
  • Patent number: 11749585
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Yiqun Bai, Vipul Mehta, John Decker, Ziyin Lin
  • Patent number: 11688634
    Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Vipul Mehta, Yiqun Bai, Ziyin Lin, John Decker, Yan Li
  • Publication number: 20230187850
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a socket that includes one or more liquid metal filled reservoirs. In selected examples, the electronic devices and sockets include configurations to aid in reducing ingress of moisture.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Ziyin Lin, Aaron Michael Garelick, Karumbu Meyyappan, Gregorio Murtagian, Srikant Nekkanty, Taylor Rawlings, Jeffory L. Smalley, Pooya Tadayon, Dingying Xu
  • Publication number: 20230187337
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes liquid metal pathways that form one or more conduction pathway through one or more dielectric layers. In selected examples, the dielectric layers are resilient, which allows for flexibility of interconnect components.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Karumbu Meyyappan, Srikant Nekkanty, Gregorio Murtagian, Pooya Tadayon, Ziyin Lin, Eric J.M. Moret, Jeffory L. Smalley, Dingying Xu
  • Patent number: 11676876
    Abstract: A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Elizabeth Nofen, Vipul Mehta, Taylor Gaines
  • Publication number: 20230089928
    Abstract: Semiconductor devices having hollow filler materials are disclosed. A disclosed example semiconductor device includes at least one of a substrate or an interposer, interconnects extending through the at least one of the substrate or the interposer, and a composite material integral with or covering at least a portion of the semiconductor device, the composite material including a polymer matrix with a hollow filler material having voids therein.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Ziyin Lin, Yiqun Bai, Hongxia Feng, Dingying Xu, Jieying Kong, Srinivas Pietambaram
  • Publication number: 20220196937
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Bassam ZIADEH, Jingyi HUANG, Yiqun BAI, Ziyin LIN, Vipul MEHTA, Joseph VAN NAUSDLE
  • Publication number: 20220165585
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.
    Type: Application
    Filed: February 10, 2022
    Publication date: May 26, 2022
    Inventors: Ziyin LIN, Vipul MEHTA, Edvin CETEGEN, Yuying WEI, Sushrutha GUJJULA, Nisha ANANTHAKRISHNAN, Shan ZHONG
  • Publication number: 20220102242
    Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
  • Patent number: 11282717
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
  • Publication number: 20210272878
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Applicant: Intel Corporation
    Inventors: Yiqun Bai, Vipul Mehta, John Decker, Ziyin Lin
  • Publication number: 20210249322
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
  • Publication number: 20210242102
    Abstract: Embodiments herein describe techniques for an IC package including an electronic component, and an underfill material around or below the electronic component to support the electronic component. The underfill material includes a resin and a thermolatent onium salt as a cationic cure for the underfill material. The thermolatent onium salt comprises an organic cation with a heteroatom center, and an anion including metalloid fluoride. The heteroatom center includes an iodonium, sulphonium, phosphonium, or N-containing onium. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Elizabeth NOFEN, Ziyin LIN, Nisha ANANTHAKRISHNAN
  • Publication number: 20210066152
    Abstract: A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Ziyin LIN, Elizabeth NOFEN, Vipul MEHTA, Taylor GAINES