Patents by Inventor Ziyin LIN
Ziyin LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250218880Abstract: Methods for fabricating glass cores with conductive vias (e.g., TGVs), as well as related devices, are disclosed. Methods described herein are based on fabricating pillars of conductive materials (e.g., metals or metal alloys) on a temporary support, inserting the pillars into corresponding via openings in a glass core, and at least partially filling the remaining space in the openings with a filler material.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Jose Waimin, Ryan Carrazzone, Bin Mu, Ziyin Lin, Yiqun Bai, Kyle Jordan Arrington, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Dingying Xu, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo
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Publication number: 20250219021Abstract: In embodiments herein, circuit components are embedded within a core layer of a substrate. The circuit components are vertically oriented within a cavity or hole of the core layer of the substrate, e.g., with conductive contacts on an edge of the component that is substantially orthogonal to a plane of the core layer. The edge that is substantially orthogonal to a plane of the core layer may be the longest edge of the component.Type: ApplicationFiled: December 27, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Bohan Shan, Ziyin Lin, Ryan Joseph Carrazzone, Hongxia Feng, Hiroki Tanaka, Haobo Chen, Yiqun Bai, Kyle J. Arrington, Jose Fernando Waimin Almendares, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Dingying Xu, Brandon Christian Marin, Clay Bradley Arrington, Yongki Min, Joseph Allen Van Nausdle, Joseph F. Walczyk, Pooya Tadayon, Mohamed R. Saber
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Publication number: 20250218906Abstract: Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Zhixin XIE, Ziqing HAN, Srinivas Venkata Ramanuja PIETAMBARAM, Jung Kyu HAN, Gang DUAN, Yingying ZHANG, Minglu LIU, Manni MO, Kyle ARRINGTON, Clay ARRINGTON, Bohan SHAN, Ryan CARRAZZONE, Yiqun BAI, Ziyin LIN, Jose WAIMIN, Dingying David XU, Hongxia FENG, Yongki MIN, Brandon C. MARIN
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Publication number: 20250220818Abstract: Embodiments disclosed herein include an apparatus with a component embedded in a core. Apparatuses disclosed herein may comprise a first component with a first surface and a second surface opposite from the first surface, where a pad is provided on the first surface. In an embodiment, a layer is over the second surface of the first component, and a second component is over the layer. In an embodiment, the second component comprises a hole that passes through at least a partial thickness of the second component.Type: ApplicationFiled: December 27, 2023Publication date: July 3, 2025Inventors: Bohan SHAN, Wei LI, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Haobo CHEN, Dingying David XU, Yongki MIN, Clay ARRINGTON, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Xiaoying GUO
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Publication number: 20250218904Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. A spacer may be included between the power components. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Ziyin Lin, Bohan Shan, Kyle J. Arrington, Ryan Joseph Carrazzone, Jose Fernando Waimin Almendares, Hongxia Feng, Srinivas Venkata Ramanuja Pietambaram, Hiroki Tanaka, Haobo Chen, Gang Duan, Brandon Christian Marin, Yongki Min, Dingying Xu, Clay Bradley Arrington, Jeremy D. Ecton, Suddhasattwa Nad
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Publication number: 20250219028Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer bonded with a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and wherein the first circuit component comprises a deep trench capacitor, and one or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Bohan Shan, Numair Ahmed, Nevin Erturk, Ziyin Lin, Ryan Carrazzone, Hongxia Feng, Hiroki Tanaka, Haobo Chen, Kyle Arrington, Jose Waimin, Srinivas Pietambaram, Gang Duan, Dingying Xu, Mohit Gupta, Brandon Marin, Xiaoying Guo, Clay Arrington
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Publication number: 20250210426Abstract: Various techniques for alleviating crack formation and propagation in glass cores of microelectronic assemblies, and related devices and methods, are disclosed. The techniques are based on including fillers into glass cores and/or in layers provided on top and/or bottom of glass cores. The fillers have at least one characteristic indicative of material's resistance to breaking under stress being higher than that of glass, which may provide reinforcement and/or increase stiffness of glass, thereby strengthening glass cores. Examples of such characteristics include material strength, fracture toughness, or elastic modulus.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Applicant: Intel CorporationInventors: Bohan Shan, Mahdi Mohammadighaleni, Hiroki Tanaka, Kyle Jordan Arrington, Yiqun Bai, Whitney Bryks, Ryan Carrazzone, Haobo Chen, Gang Duan, Jeremy Ecton, Hongxia Feng, Xiaoying Guo, Shayan Kaviani, Ziyin Lin, Brandon C. Marin, Robert Alan May, Bin Mu, Bai Nie, Ala Omer, Srinivas Venkata Ramanuja Pietambaram, Dilan Seneviratne, Jose Waimin, Dingying Xu, Ehsan Zamani
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Publication number: 20250183182Abstract: Various techniques for alleviating (e.g., mitigating or reducing) stresses between glass core materials and electrically conductive materials deposited in through-glass vias (TGVs) and related devices and methods are disclosed. In one aspect, a microelectronic assembly includes a glass core having a first face and a second face opposite the first face, and a TGV extending through the glass core between the first face and the second face, wherein the TGV includes a conductive material and a buffer layer between the conductive material and the glass core, wherein a CTE of the buffer layer is smaller than a CTE of the conductive material.Type: ApplicationFiled: November 30, 2023Publication date: June 5, 2025Inventors: Bohan Shan, Mahdi Mohammadighaleni, Joshua Stacey, Ehsan Zamani, Aaditya Candadai, Jacob Vehonsky, Daniel Wandera, Mitchell Page, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jeremy Ecton, Brandon C. Marin, Onur Ozkan, Vinith Bejugam, Dhruba Pattadar, Amm Hasib, Nicholas Haehn, Makoyi Watson, Sanjay Tharmarajah, Jason M. Gamba, Yuqin Li, Astitva Tripathi, Mohammad Mamunur Rahman, Haifa Hariri, Shayan Kaviani, Logan Myers, Darko Grujicic, Elham Tavakoli, Whitney Bryks, Dilan Seneviratne, Bainye Angoua, Peumie Abeyratne Kuragama, Hongxia Feng, Kyle Jordan Arrington, Bai Nie, Jose Waimin, Ryan Carrazzone, Haobo Chen, Dingying Xu, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Bin Mu, Thomas S. Heaton, Rahul N. Manepalli
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Publication number: 20250183180Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.Type: ApplicationFiled: December 5, 2023Publication date: June 5, 2025Inventors: Brandon C. MARIN, Robert Alan MAY, Minglu LIU, Bohan SHAN, Jason M. GAMBA, Lilia MAY, Tarek A. IBRAHIM, Hiroki TANAKA, Srinivas Venkata Ramanuja PIETAMBARAM, Jeremy D. ECTON, Gang DUAN, Suddhasattwa NAD, Benjamin DUONG, Haobo CHEN, Xiao LIU, Xiyu HU, Wei WEI, Bai NIE, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Dingying David XU, Bin MU, Mohit GUPTA, Xiaoying GUO, Yiqun BAI
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Publication number: 20250149414Abstract: Embodiments disclosed herein include an interconnect structure. In an embodiment, the interconnect structure is an apparatus that comprises a substrate with a well through a thickness of the substrate. In an embodiment, the substrate comprises a polymer foam. In an embodiment, a liquid metal is in the opening, and the liquid metal comprises voids.Type: ApplicationFiled: November 8, 2023Publication date: May 8, 2025Inventors: Ziyin LIN, Karumbu MEYYAPPAN, Gregorio R. MURTAGIAN, Dingying David XU
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Publication number: 20250110295Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Ziyin Lin, Saikumar Jayaraman, Yiqun Bai, Fan Fan, Dingying Xu
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Publication number: 20250112085Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Bohan Shan, Ziyin Lin, Haobo Chen, Yiqun Bai, Kyle Arrington, Jose Waimin, Ryan Carrazzone, Hongxia Feng, Dingying Xu, Srinivas Pietambaram, Minglu Liu, Seyyed Yahya Mousavi, Xinyu Li, Gang Duan, Wei Li, Bin Mu, Mohit Gupta, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo, Ashay Dani
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Publication number: 20250112161Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Minglu Liu, Seyyed Yahya Mousavi, Yingying Zhang, Gang Duan, Andrey Gunawan, Yosuke Kanaoka, Yiqun Bai, Ziyin Lin, Bohan Shan, Dingying Xu, Srinivas Pietambaram, Hong Seung Yeon
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Publication number: 20250112164Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Onur OZKAN, Ryan CARRAZZONE, Rui ZHANG, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Venkata Rajesh SARANAM, Shripad GOKHALE, Kartik SRINIVASAN, Edvin CETEGEN, Mine KAYA, Nicholas S. HAEHN, Deniz TURAN
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250106983Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Inventors: Bohan SHAN, Kyle ARRINGTON, Dingying David XU, Ziyin LIN, Timothy GOSSELIN, Elah BOZORG-GRAYELI, Aravindha ANTONISWAMY, Wei LI, Haobo CHEN, Yiqun BAI, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Ashay DANI
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Publication number: 20250102744Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Applicant: Intel CorporationInventors: Feifei Cheng, Kumar Abhishek Singh, Peter A. Williams, Ziyin Lin, Fan Fan, Yang Wu, Saikumar Jayaraman, Baris Bicen, Darren Vance, Anurag Tripathi, Divya Pratap, Stephanie J. Arouh
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Publication number: 20250105074Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.Type: ApplicationFiled: December 11, 2024Publication date: March 27, 2025Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Wei Wei, Jose Fernando Waimin Almendares, Ryan Joseph Carrazzone, Kyle Jordan Arrington, Ziyin Lin, Dingying Xu, Hongxia Feng, Yiqun Bai, Hiroki Tanaka, Brandon Christian Marin, Jeremy Ecton, Benjamin Taylor Duong, Gang Duan, Srinivas Venkata Ramanuja Pietambaram, Rui Zhang, Mohit Gupta
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Publication number: 20250079278Abstract: In one embodiment, an apparatus comprises a substrate with conductive contacts on a first side of the substrate and a housing coupled to the first side of the substrate. The housing defines a set of holes around the conductive contacts. The apparatus further includes Gallium-based liquid metal in each hole, with the liquid metal being in contact with the conductive contact of the hole. The apparatus further includes a passivation layer on a surface of the liquid metal in each hole, the passivation layer being on an opposite end of the hole from the conductive contact in the hole.Type: ApplicationFiled: September 1, 2023Publication date: March 6, 2025Applicant: Intel CorporationInventors: Karumbu Nathan Meyyappan, Pooya Tadayon, Ziyin Lin, Gregory A. Stone
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Publication number: 20240402445Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 8, 2024Publication date: December 5, 2024Inventors: Bassam ZIADEH, Jingyi HUANG, Yiqun BAI, Ziyin LIN, Vipul MEHTA, Joseph VAN NAUSDLE
