Patents by Inventor Ziyin LIN

Ziyin LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250106983
    Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Inventors: Bohan SHAN, Kyle ARRINGTON, Dingying David XU, Ziyin LIN, Timothy GOSSELIN, Elah BOZORG-GRAYELI, Aravindha ANTONISWAMY, Wei LI, Haobo CHEN, Yiqun BAI, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Ashay DANI
  • Publication number: 20250102744
    Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Kumar Abhishek Singh, Peter A. Williams, Ziyin Lin, Fan Fan, Yang Wu, Saikumar Jayaraman, Baris Bicen, Darren Vance, Anurag Tripathi, Divya Pratap, Stephanie J. Arouh
  • Publication number: 20250105074
    Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Wei Wei, Jose Fernando Waimin Almendares, Ryan Joseph Carrazzone, Kyle Jordan Arrington, Ziyin Lin, Dingying Xu, Hongxia Feng, Yiqun Bai, Hiroki Tanaka, Brandon Christian Marin, Jeremy Ecton, Benjamin Taylor Duong, Gang Duan, Srinivas Venkata Ramanuja Pietambaram, Rui Zhang, Mohit Gupta
  • Publication number: 20250079278
    Abstract: In one embodiment, an apparatus comprises a substrate with conductive contacts on a first side of the substrate and a housing coupled to the first side of the substrate. The housing defines a set of holes around the conductive contacts. The apparatus further includes Gallium-based liquid metal in each hole, with the liquid metal being in contact with the conductive contact of the hole. The apparatus further includes a passivation layer on a surface of the liquid metal in each hole, the passivation layer being on an opposite end of the hole from the conductive contact in the hole.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Applicant: Intel Corporation
    Inventors: Karumbu Nathan Meyyappan, Pooya Tadayon, Ziyin Lin, Gregory A. Stone
  • Publication number: 20240402445
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Inventors: Bassam ZIADEH, Jingyi HUANG, Yiqun BAI, Ziyin LIN, Vipul MEHTA, Joseph VAN NAUSDLE
  • Publication number: 20240388018
    Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a first surface and a second surface opposite from the first surface. In an embodiment, pads are on the first surface of the package substrate, where the pads have a first width. In an embodiment, a layer is on the first surface of the package substrate, where the layer comprises wells through the layer, and where the wells have a second width that is wider than the first width. In an embodiment, a liquid metal is in the wells and in contact with the pads.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: Karumbu MEYYAPPAN, Gregorio R. MURTAGIAN, Ziyin LIN
  • Publication number: 20240363520
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a substrate with a layer on the substrate. In an embodiment, the layer comprises a plurality of wells. In an embodiment, a liquid metal is in the plurality of wells. In an embodiment, a cap is on the layer to seal the plurality of wells, where the cap comprises a polymer, and fibers within the polymer.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Inventors: Ziyin LIN, Boer LIU, Dingying David XU, Karumbu MEYYAPPAN
  • Patent number: 12130482
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Bassam Ziadeh, Jingyi Huang, Yiqun Bai, Ziyin Lin, Vipul Mehta, Joseph Van Nausdle
  • Publication number: 20240332125
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a first layer and a second layer over the first layer. In an embodiment, the second layer comprises a dielectric material including sulfur. In an embodiment, fillers are within the second layer. In an embodiment, the fillers have a volume fraction that is less than approximately 0.2.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: Kyle ARRINGTON, Clay ARRINGTON, Bohan SHAN, Haobo CHEN, Srinivas V. PIETAMBARAM, Gang DUAN, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying XU, Bai NIE
  • Publication number: 20240312865
    Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Kyle Arrington, Bohan Shan, Haobo Chen, Bai Nie, Srinivas Pietambaram, Gang Duan, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
  • Patent number: 12068222
    Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
  • Publication number: 20240270929
    Abstract: Capillary underfill formulations that may include fillers. The fillers may include carbon nanotubes, such as surface functionalized carbon nanotubes. Methods for forming capillary underfill materials that may have improved fracture toughness, reduced crack propagation, and a reduced likelihood of delamination. The surface functionalized carbon nanotubes may include amine functionalized carbon nanotubes. Containers, such as syringes, that may have a reservoir in which a capillary underfill formulation is disposed.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 15, 2024
    Inventors: Clay Arrington, Kyle Arrington, Ziyin Lin, Jose Waimin, Dingying Xu
  • Publication number: 20240219656
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20240219654
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20240219660
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Yiqun Bai, Dingying Xu, Eric J.M. Moret, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Bin Mu
  • Publication number: 20240222259
    Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Haobo Chen, Bohan Shan, Xiyu Hu, Rhonda Jack, Catherine Mau, Hongxia Feng, Xiao Liu, Wei Wei, Srinivas Pietambaram, Gang Duan, Xiaoying Guo, Dingying Xu, Kyle Arrington, Ziyin Lin, Hiroki Tanaka, Leonel Arana
  • Publication number: 20240222243
    Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240222210
    Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240222257
    Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Ziyin Lin, Rahul N. Manepalli, Brandon C. Marin, Jeremy D. Ecton
  • Publication number: 20240222301
    Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Dingying Xu, Sairam Agraharam, Ashay Dani, Eric J. M. Moret, Tarek Ibrahim