Abstract: The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

Abstract: A method and an apparatus for testing a chip, as well as a storage medium, and a chip thereof are provided. The chip includes an operation module. The method includes receiving, via a first pin of the chip, a test control signal indicating a test type of the operation module; performing a first test for the operation module using a first test vector based on the test type; or performing a second test for the operation module using a second test vector, where the first test is a test for the memory included in the operation module and the second test is a test for the functional logic in included in the operation module.

Abstract: Methods, apparatuses and electronic devices for testing a memory of a chip are provided. Specifically, the chip includes a plurality of operation modules, the operation module includes at least one operation unit, and the operation unit includes at least one memory. The method includes generating a first test vector for a first operation module of the operation modules, and testing the memory in the first operation module by using the generated first test vector independent of other operation modules of plurality of operation modules, where the other operation modules are different from the first operation module.

Abstract: A wireless transmission parameter adjustment method and a related device. The method includes monitoring a frequency parameter of a cell, determining, in response to detecting that the frequency parameter of the cell increases, a location relationship between a first terminal and an access network device, wherein the first terminal is a terminal camping on the cell, and adjusting a target power parameter of the first terminal according to the location relationship between the first terminal and the access network device, so that a radio remote unit power does not exceed a preset power, where the target power parameter is a power parameter other than a cell-specific reference signal power.

Abstract: The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

Abstract: A method and an apparatus for testing a chip, as well as a storage medium, and a chip thereof are provided. The chip includes an operation module. The method includes receiving, via a first pin of the chip, a test control signal indicating a test type of the operation module; performing a first test for the operation module using a first test vector based on the test type; or performing a second test for the operation module using a second test vector, where the first test is a test for the memory included in the operation module and the second test is a test for the functional logic in included in the operation module.

Abstract: Methods, apparatuses and electronic devices for testing a memory of a chip are provided. Specifically, the chip includes a plurality of operation modules, the operation module includes at least one operation unit, and the operation unit includes at least one memory. The method includes generating a first test vector for a first operation module of the operation modules, and testing the memory in the first operation module by using the generated first test vector independent of other operation modules of plurality of operation modules, where the other operation modules are different from the first operation module.

Abstract: A wireless transmission parameter adjustment method and a related device. The method includes monitoring a frequency parameter of a cell, determining, in response to detecting that the frequency parameter of the cell increases, a location relationship between a first terminal and an access network device, wherein the first terminal is a terminal camping on the cell, and adjusting a target power parameter of the first terminal according to the location relationship between the first terminal and the access network device, so that a radio remote unit power does not exceed a preset power, where the target power parameter is a power parameter other than a cell-specific reference signal power.

Abstract: A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.

Abstract: A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.