Abstract: An example holographic video recording system comprises: a first group of cameras positioned at a first position, a second group of cameras positioned at a second position, and a third group of cameras including a third infrared camera. The first group of cameras includes a first infrared camera and a first color camera; the second group of cameras includes a second infrared camera and a second color camera; and the third group of cameras includes a third infrared camera spatially positioned between the first and second infrared cameras. A depth map may be calculated using the first infrared camera and the second infrared camera in accordance with determining that an object is beyond a predefined distance from the holographic video recording system; or the first infrared camera and the third infrared camera in accordance with determining that the object is within the predefined distance from the holographic video recording system.

Abstract: A mobile device comprises: a mesh loader manages configured to download compressed mesh sequences from a remote server into a local storage buffer; a mesh decoder that is configured to decode compressed mesh sequences into frames of meshes in real-time; a mesh decoder manager that is configured to request compressed mesh sequences from the mesh loader and to request the mesh decoder to decode the compressed mesh sequences; a player manager that is configured to decode texture video and to request corresponding decoded mesh from the mesh decoder manager and to maintain synchronizations between requesting the corresponding decoded mesh and decoding the texture video; and a renderer that is configured to render, using a rendering engine, the decoded mesh on a canvas; and a camera controller that is configured to detect one or more user actions and control a hardware camera in accordance with the one or more user actions.

Abstract: An example holographic video recording system comprises: a first group of cameras positioned at a first position, a second group of cameras positioned at a second position, and a third group of cameras including a third infrared camera. The first group of cameras includes a first infrared camera and a first color camera; the second group of cameras includes a second infrared camera and a second color camera; and the third group of cameras includes a third infrared camera spatially positioned between the first and second infrared cameras. A depth map may be calculated using the first infrared camera and the second infrared camera in accordance with determining that an object is beyond a predefined distance from the holographic video recording system; or the first infrared camera and the third infrared camera in accordance with determining that the object is within the predefined distance from the holographic video recording system.

Abstract: An example holographic video recording system comprises: a first group of cameras positioned at a first position, a second group of cameras positioned at a second position, and a third group of camera including a third infrared camera. The first group of cameras includes a first infrared camera and a first color camera; the second group of cameras includes a second infrared camera and a second color camera; and the third group of camera includes a third infrared camera spatially positioned between the first and second infrared cameras. A depth map may be calculated using the first infrared camera and the second infrared camera in accordance with determining that an object is beyond a predefined distance from the holographic video recording system; or the first infrared camera and the third infrared camera in accordance with determining that the object is within the predefined distance from the holographic video recording system.

Abstract: A mobile device comprises: a mesh loader manages configured to download compressed mesh sequences from a remote server into a local storage buffer; a mesh decoder that is configured to decode compressed mesh sequences into frames of meshes in real-time; a mesh decoder manager that is configured to request compressed mesh sequences from the mesh loader and to request the mesh decoder to decode the compressed mesh sequences; a player manager that is configured to decode texture video and to request corresponding decoded mesh from the mesh decoder manager and to maintain synchronizations between requesting the corresponding decoded mesh and decoding the texture video; and a renderer that is configured to render, using a rendering engine, the decoded mesh on a canvas; and a camera controller that is configured to detect one or more user actions and control a hardware camera in accordance with the one or more user actions.

Abstract: An example holographic video recording system comprises: a first group of cameras positioned at a first positon, a second group of cameras positioned at a second positon, and a third group of camera including a third infrared camera. The first group of cameras includes a first infrared camera and a first color camera; the second group of cameras includes a second infrared camera and a second color camera; and the third group of camera includes a third infrared camera spatially positioned between the first and second infrared cameras. A depth map may be calculated using the first infrared camera and the second infrared camera in accordance with determining that an object is beyond a predefined distance from the holographic video recording system; or the first infrared camera and the third infrared camera in accordance with determining that the object is within the predefined distance from the holographic video recording system.

Abstract: The latest High Efficiency Video Coding (HEVC) standard achieves significant compression efficiency improvement over the H.264 standard, at a much higher cost of computational complexity. A framework for software-based H.264 to HEVC transcoding on multicore processors and distributed systems is provided. By utilizing information extracted from the input H.264 bitstream, the transcoding process can be accelerated at a high ratio with modest visual quality loss. Wavefront Parallel Processing (WPP) and SIMD acceleration are also implemented to improve the trans coding efficiency on multi-core processors with SIMD instruction set extensions. Based on the HEVC HM 12.0 reference software and using standard HEVC test bitstreams, the proposed transcoder can achieve around 120× speed up over decoding and re-encoding based on ffmpeg and the HM software without significant R-D performance loss.

Abstract: The emerging High Efficiency Video Coding (HEVC) standard achieves significant performance improvement over H.264/AVC standard at a cost of much higher complexity. An H.264/AVC to HEVC transcoder is described for multi-core processors implementing Wavefront Parallel Processing (WPP) and SIMD acceleration, along with expedited motion estimation (ME) and mode decision (MD) by utilizing information extracted from the input H.264/AVC stream. Experiments using standard HEVC test bitstreams show that the described transcoder may achieve a 70× speed up over the HEVC HM S.1 reference software (including H.264 encoding) at very small rate distortion (RD) performance loss.

Abstract: The latest High Efficiency Video Coding (HEVC) standard achieves significant compression efficiency improvement over the H.264 standard, at a much higher cost of computational complexity. A framework for software-based H.264 to HEVC transcoding on multicore processors and distributed systems is provided. By utilizing information extracted from the input H.264 bitstream, the transcoding process can be accelerated at a high ratio with modest visual quality loss. Wavefront Parallel Processing (WPP) and SIMD acceleration are also implemented to improve the trans coding efficiency on multi-core processors with SIMD instruction set extensions. Based on the HEVC HM 12.0 reference software and using standard HEVC test bitstreams, the proposed transcoder can achieve around 120× speed up over decoding and re-encoding based on ffmpeg and the HM software without significant R-D performance loss.

Abstract: The emerging High Efficiency Video Coding (HEVC) standard achieves significant performance improvement over H.264/AVC standard at a cost of much higher complexity. An H.264/AVC to HEVC transcoder is described for multi-core processors implementing Wavefront Parallel Processing (WPP) and SIMD acceleration, along with expedited motion estimation (ME) and mode decision (MD) by utilizing information extracted from the input H.264/AVC stream. Experiments using standard HEVC test bitstreams show that the described transcoder may achieve a 70× speed up over the HEVC HM S.1 reference software (including H.264 encoding) at very small rate distortion (RD) performance loss.

Abstract: A circuit and a method for implementing Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are provided.

Abstract: A circuit and a method for parallel perforation in rate matching can adopt three selector arrays and three register groups. The first selector array is configured to remove null bits in input data and output the remaining data to the first register group; the second selector array is configured to combine the first register group and the third register group and then output the combined data to the second register group; during the combination, the valid data in the third register group are preferentially selected, and then the data in the first register group are selected; Further, the third selector array is configured to output remaining valid data in the first selector group to the third register group if the valid data in the first selector group are not used out while combining the first register group and the third register group by the second selector array.

Abstract: The present invention discloses a circuit and a method for parallel perforation in rate matching, which can reduce the perforation processing time delay to satisfy the requirements of a Long Term Evolution (LTE). Both the circuit and the method can adopt three selector arrays and three register groups. Specifically, the first selector array is configured to remove null bits in input data and output the remaining data to the first register group; the second selector array is configured to combine the first register group and the third register group and then output the combined data to the second register group; during the combination, the valid data in the third register group are preferentially selected, and then the data in the first register group are selected; when the second register group is full, the data therein are output to the exterior as the results of the perforation processing.

Abstract: A circuit and a method for implementing Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are provided.