Patents by Inventor Zlata Kovac

Zlata Kovac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7368818
    Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: May 6, 2008
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig S. Mitchell, Thomas H. DiStefano, John W. Smith
  • Publication number: 20060049498
    Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.
    Type: Application
    Filed: October 26, 2005
    Publication date: March 9, 2006
    Applicant: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas DiStefano, John Smith
  • Publication number: 20050139986
    Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.
    Type: Application
    Filed: February 24, 2005
    Publication date: June 30, 2005
    Applicant: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas Distefano, John Smith
  • Patent number: 6870272
    Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: March 22, 2005
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas Distefano, John Smith
  • Patent number: 6723584
    Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure such as a flexible dielectric sheet having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. A platen is provided in engagement with a second surface of the first support structure. The first surface of a second support structure, such as a semiconductor wafer, is abutted against the porous layer and, after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may be at least partially cured.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: April 20, 2004
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas Distefano, John Smith
  • Patent number: 6525429
    Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure, such as a flexible dielectric sheet, having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. The first surface of a second support structure, such as a semiconductor wafer, is then abutted against the porous layer and, desirably after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may then be at least partially cured.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: February 25, 2003
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas Distefano, John Smith
  • Publication number: 20030027374
    Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure, such as a flexible dielectric sheet, having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. The first surface of a second support structure, such as a semiconductor wafer, is then abutted against the porous layer and, desirably after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may then be at least partially cured.
    Type: Application
    Filed: September 26, 2002
    Publication date: February 6, 2003
    Inventors: Zlata Kovac, Craig S. Mitchell, Thomas H. DiStefano, John W. Smith
  • Publication number: 20020109213
    Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure, such as a flexible dielectric sheet, having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. The first surface of a second support structure, such as a semiconductor wafer, is then abutted against the porous layer and, desirably after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may then be at least partially cured.
    Type: Application
    Filed: April 16, 2002
    Publication date: August 15, 2002
    Inventors: Zlata Kovac, Craig S. Mitchell, Thomas H. DiStefano, John W. Smith
  • Patent number: 6373141
    Abstract: A microelectronic package comprising a microelectronic element, resilient element including one or more intermediary layers capable of being wetted and assembled with the microelectronic element, and an adhesive is provided. The adhesive contacts at least one of the one or more intermediary layers and the microelectronic element. A resilient element is also provided.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: April 16, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Zlata Kovac, John W. Smith
  • Patent number: 6370032
    Abstract: The present invention provides an interconnection scheme having complaint contacts arranged in an array to connect conductive surfaces on a microelectronic device and a supporting substrate, such as a printed circuit board. This invention accommodates for the difference in thermal coefficients of expansion between the device and the supporting substrate. Typically, an area array of conductive contact pads are connected into rows by conductive leads on a flexible, intermediate substrate. Each of the conductive leads bridges a bonding hole in the intermediate substrate which is situated between successive contact pads. Each of the conductive leads further has a frangible portion within or near each bonding hole. A stand-off between the intermediate substrate and the device is create by compliant dielectric pads, typically composed of an elastomer material, positioned under each contact pad.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: April 9, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Zlata Kovac, Konstantine Karavakis
  • Patent number: 6274820
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts expand radially and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by conductive bonding material carried on the contacts themselves.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: August 14, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine N. Karavakis, Zlata Kovac, Joseph Fjelstad
  • Patent number: 6266874
    Abstract: A method of making a microelectronic component by providing a conductive element, providing a resist at selected locations on said conductive element and electrophoretically depositing an uncured dielectric material on the conductive element, wherein the uncured material will be deposited on the conductive element except at locations covered by the resist. The deposited material is cured to form a dielectric layer and the resist is removed so that the dielectric layer has openings extending to the conductive element at locations the locations which were covered by the resist.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: July 31, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine N. Karavakis, Zlata Kovac, Joseph Fjelstad
  • Patent number: 6255738
    Abstract: Filled, curable siloxane encapsulant compositions containing a curable siloxane base resin with functional groups reactive with functional groups of a hardener compound to form a polysiloxane, and filler particles with surface functional groups reactive with the hardener compound functional groups, wherein the filler particles have at least a bi-modal particle packing distribution of first filler particles having a first diameter and second filler particles having a second diameter smaller than the first diameter, and the first and second filler particles are present in amounts effective to provide a particle packing distribution with a relative bulk volume of at least about 90 percent.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: July 3, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Craig Mitchell, Mark Thorson, Zlata Kovac
  • Patent number: 6239386
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts expand radially and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by conductive bonding material carried on the contacts themselves.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: May 29, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine N. Karavakis, Zlata Kovac, Joseph Fjelstad
  • Patent number: 6202299
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
  • Patent number: 6133639
    Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: October 17, 2000
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas H. Distefano, John W. Smith
  • Patent number: 6045655
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: April 4, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
  • Patent number: 6030856
    Abstract: A method of making a microelectronic package includes providing first and second microelectronic elements having electrically conductive parts and disposing a resilient element having one or more intermediary layers capable of being wetted by an adhesive between the microelectronic elements. The resilient element includes fibrous material, a fibrous matrix and/or voids formed at the intermediary layers thereof. An adhesive is provided between the intermediary layers and the microelectronic elements. The adhesive is then cured while it remains in contact with the intermediary layers for bonding the resilient element and the microelectronic elements. The electrically conductive parts are then bonded together to form electrical interconnections. A microelectronic package comprising a resilient element including one or more intermediary layers capable of being wetted by an adhesive is also provided.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: February 29, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Zlata Kovac, John W. Smith
  • Patent number: 6012224
    Abstract: The present invention provides an interconnection scheme having compliant contacts arranged in an array to connect conductive surfaces on a microelectronic device and a supporting substrate, such as a printed circuit board. This invention accommodates for the difference in thermal coefficients of expansion between the device and the supporting substrate. Typically, an area array of conductive contact pads are connected into rows by conductive leads on a flexible, intermediate substrate. Each of the conductive leads bridges a bonding hole in the intermediate substrate which is situated between successive contact pads. Each of the conductive leads further has a frangible portion within or near each bonding hole. A stand-off between the intermediate substrate and the device is create by compliant dielectric pads, typically composed of an elastomer material, positioned under each contact pad.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: January 11, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Zlata Kovac, Konstantine Karavakis
  • Patent number: 5875545
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: March 2, 1999
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell