Abstract: This data-processing device includes a unit for processing data, a storage memory and a buffer-memory device configured to contain a first group of data relative to a first context and exchange data between the processing unit and the first group of data. The buffer-memory device is further configured to contain a second group of data relative to a second context and, upon reception of a context-switching instruction, exchange data between the processing unit and the second group of data, in place of the first group of data. The data-processing device further includes a context-switching device configured to emit the context-switching instruction, select a group of data recorded in the storage memory, copy the first group of data to the storage memory and copy the selected group of data to the buffer-memory device.

Abstract: A method for communication between first and second devices includes the following stages: the first device sends a request to the second device; the second device receives the request; the second device sends the first device a response to the request; the first device receives the response; the second device estimates a period after which it will be able to send the response, as well as, in at least some cases, the following steps: before sending the response, the second device sends an acknowledgement to the first device, the acknowledgement including the estimated period; the first device receives the acknowledgement; the first device calculates a time interval based on the estimated period; the first device allows the time interval to elapse before starting to monitor the arrival of messages to detect the arrival of the response.

Abstract: This data-processing device includes a unit for processing data, a storage memory and a buffer-memory device configured to contain a first group of data relative to a first context and exchange data between the processing unit and the first group of data. The buffer-memory device is further configured to contain a second group of data relative to a second context and, upon reception of a context-switching instruction, exchange data between the processing unit and the second group of data, in place of the first group of data. The data-processing device further includes a context-switching device configured to emit the context-switching instruction, select a group of data recorded in the storage memory, copy the first group of data to the storage memory and copy the selected group of data to the buffer-memory device.

Abstract: A data-processing system (DTS) includes a central hardware unit (CPU) and an additional hardware unit (HW), the central hardware unit (CPU) being adapted to execute a task by a processing thread (TM), and to trigger offloading of execution of a first part (P1a, P1b, P2) of the task to the additional hardware unit (HW); and wherein the additional hardware unit is adapted to call on functionalities of the central hardware unit (CPU), triggered by the first part, and the central hardware unit (CPU) executes a second part (P2) of the task forming a sub-part of the first part by a service processing thread (TS).

Abstract: A computer device with synchronization barrier including a memory and a processing unit capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, the blocks being associated by groups in successive work steps. The device further includes a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Abstract: The dynamic monitoring of distances, in particular of memory access distances, in a non-uniform memory access (NUMA) type system comprising a plurality of processors, and a local memory being associated with each processor of the plurality of processors is disclosed. In one aspect, after having obtained at least one NUMA distance between at least one first processor of the plurality of processors and a local memory associated with at least one second processor of the plurality of processors, the at least one NUMA distance obtained is stored in place of at least one NUMA distance, previously stored, between the at least one first processor and the local memory associated with the at least one second processor, the at least one NUMA distance stored being usable directly by the operating system of the NUMA type system.

Abstract: A data-processing system (DTS) includes a central hardware unit (CPU) and an additional hardware unit (HW), the central hardware unit (CPU) being adapted to execute a task by a processing thread (TM), and to trigger offloading of execution of a first part (P1a, P1b, P2) of the task to the additional hardware unit (HW); and wherein the additional hardware unit is adapted to call on functionalities of the central hardware unit (CPU), triggered by the first part, and the central hardware unit (CPU) executes a second part (P2) of the task forming a sub-part of the first part by a service processing thread (TS).

Abstract: A process manager (36) comprises a process data memory (44), and a process processing unit (38), capable of causing a process code to be executed in interaction with a designated part of this memory. The processing unit (38) is capable of establishing a super-process associated with a designated part of the memory (42) suitable to house the data from one or more processes (34), and is capable of causing the code of each of these processes (34) to be executed in separate interaction with their data. This manager (36) comprises a pooling function (40) organized to load incident processes (34) into a super-process in response to a condition affecting at least in part these incident processes. The processing unit (38) is organized to house incident processes in a super-process in response to a condition affecting the incident processes.

Abstract: Managing memory access in a non-uniform memory access (NUMA) multiprocessor architecture including two computation units and at least two separate memories is disclosed. Each memory, including at least one logic memory entity, is locally associated with a computation unit. After receiving a control for access to a logic memory entity, the status of an indicator of the status of the logic memory entity (first entity) to which the received command applies is determined. If the indicator is in a first state, the received control is executed. If, on the contrary, the indicator is in a second state, data stored in the first entity is migrated into a second logic memory entity of a memory separate from the memory including the first entity, and the status of the second entity is placed into the first state.

Abstract: The present invention relates to a computer device with synchronization barrier. The device comprises a memory and a processing unit, capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, said blocks being associated by groups in successive work steps, The device further comprises a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Abstract: A process manager (36) comprises a process data memory (44), and a process processing unit (38), capable of causing a process code to be executed in interaction with a designated part of this memory. The processing unit (38) is capable of establishing a super-process associated with a designated part of the memory (42) suitable to house the data from one or more processes (34), and is capable of causing the code of each of these processes (34) to be executed in separate interaction with their data. This manager (36) comprises a pooling function (40) organized to load incident processes (34) into a super-process in response to a condition affecting at least in part these incident processes. The processing unit (38) is organized to house incident processes in a super-process in response to a condition affecting the incident processes.

Abstract: The invention relates to a process for dynamically reconfiguring an information processing system (1), particularly a so-called “SMP” symmetric multiprocessor system. The process comprises a preliminary step for detecting a failure risk of one of the components of the system (CPU3). Following this detection, the system (1) is placed in a coherent, so-called “frozen” state in a first step with the aid of programs (J1-J4) executing specific tasks. A second step consists of reconfiguring the system by reallocating/de-allocating all or some of the components (CPU1-CPU4). In a third step, the component (CPU3) that presents a failure risk is isolated. The pending interruptions (4) are processed and the current tasks (6) are executed prior to the “freeze.” Likewise, the queues of tasks to be executed are purged prior to the “freeze.” Then, the subsequent tasks and interrupts are inhibited until a final step that consists of releasing the system (1).

Abstract: In a computer platform (PF) comprising at least one unit (M1, M2), each including at least one respective processor (PRO1-PRO2, PRO3-PRO5) and at least one respective interrupt controller (CI1, CI2), and an operating system (SE) including a basic kernel (NOY) for creating extension modules external to said basic kernel, at least one interrupt managing extension module (MEX1, MEX2) external to the basic kernel (NOY) is created in order to relieve the basic kernel of the management of interruptions.

Abstract: The invention relates to an architecture for management of vital data in a multi-module digital data processing machine (1) and the process for its implementation. Each module (M1 through Mn) comprises a physical nonvolatile memory (NVM1 through NVMn) in which vital data is stored. A first area (G1 through Gx) stores global vital data obtained by copying and associated with the operation of the machine (1). A second area (L1 through Lx) stores local vital data associated with the operation of the module (M1 through Mn). A virtual nonvolatile memory in two parts, global memory and local memory divided into windows, makes it possible, under the control of an extension of the operating system, to address the physical nonvolatile memories (NVM1 through NVMn). The windows of a defective module (M1 through Mn) are not visible. At the startup, a specific firmware determines the state of the modules (M1 through Mn).

Abstract: In a computer platform (PF) comprising at least one unit (M1, M2), each including at least one respective processor (PRO1-PRO2, PRO3-PRO5) and at least one respective interrupt controller (CI1, CI2), and an operating system (SE) including a basic kernel (NOY) for creating extension modules external to said basic kernel, at least one interrupt managing extension module (MEX1, MEX2) external to the basic kernel (NOY) is created in order to relieve the basic kernel of the management of interruptions.

Abstract: The invention relates to a method of correction of corrupted data stored in a memory location by scrubbing. The memory is associated with an error correcting code device which corrects the data transmitted to a user requesting them. The method comprises three steps. During a first step, the data is read from the memory at an address contained in a first register, corrected, and stored into a second register. A reservation is created. During a second step, if a reservation exists the data contained in the second register is written back into the same memory location. The reservation is cleared and a particular field of a condition register is modified. If a reservation does not exist, the second step is completed without altering the memory location. During the third step, the status of the condition register is checked. If the test is positive the process is ended, the scrubbing being successful; if not, an iteration of the three above steps is executed.