Patents by Inventor Zoltan Ring
Zoltan Ring has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11316028Abstract: Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.Type: GrantFiled: February 7, 2011Date of Patent: April 26, 2022Assignee: Wolfspeed, Inc.Inventors: Scott T. Sheppard, Richard Peter Smith, Zoltan Ring
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Patent number: 10367074Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: September 26, 2016Date of Patent: July 30, 2019Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 9934983Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.Type: GrantFiled: February 3, 2014Date of Patent: April 3, 2018Assignee: Cree, Inc.Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
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Patent number: 9812338Abstract: Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm2). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.Type: GrantFiled: March 14, 2013Date of Patent: November 7, 2017Assignee: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Daniel Namishia
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Patent number: 9761439Abstract: A semiconductor device includes a plasma-enhanced chemical vapor deposition (PECVD) protective layer configured to prevent failure of the semiconductor device throughout a temperature humidity with bias (THB) test exceeding about 1000 hours and/or a highly accelerated stress test (HAST) exceeding about 96 hours. Including a PECVD protective layer capable of protecting the semiconductor device throughout a THB test exceeding about 1000 hours and/or a HAST exceeding about 96 hours results in an extremely robust device, while providing the protective layer via PECVD results in convenience and cost savings.Type: GrantFiled: December 12, 2014Date of Patent: September 12, 2017Assignee: Cree, Inc.Inventors: Zoltan Ring, Sei-Hyung Ryu, Daniel Namishia
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Patent number: 9607955Abstract: The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.Type: GrantFiled: November 10, 2010Date of Patent: March 28, 2017Assignee: Cree, Inc.Inventors: Van Mieczkowski, Zoltan Ring, Jason Gurganus, Helmut Hagleitner
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Publication number: 20170012106Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 9530647Abstract: Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width. A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess.Type: GrantFiled: September 25, 2013Date of Patent: December 27, 2016Assignee: Cree, Inc.Inventors: Zoltan Ring, Dan Namishia
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Patent number: 9490169Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: November 2, 2010Date of Patent: November 8, 2016Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Publication number: 20160172315Abstract: A semiconductor device includes a plasma-enhanced chemical vapor deposition (PECVD) protective layer configured to prevent failure of the semiconductor device throughout a temperature humidity with bias (THB) test exceeding about 1000 hours and/or a highly accelerated stress test (HAST) exceeding about 96 hours. Including a PECVD protective layer capable of protecting the semiconductor device throughout a THB test exceeding about 1000 hours and/or a HAST exceeding about 96 hours results in an extremely robust device, while providing the protective layer via PECVD results in convenience and cost savings.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventors: Zoltan Ring, Sei-Hyung Ryu, Daniel Namishia
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Patent number: 9269662Abstract: A semiconductor die, which includes a substrate, a group of primary conduction sub-layers, and a group of separation sub-layers, is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers.Type: GrantFiled: October 17, 2012Date of Patent: February 23, 2016Assignee: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Daniel Namishia, Fabian Radulescu
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Patent number: 9142631Abstract: Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300° C. and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300° C.Type: GrantFiled: March 17, 2010Date of Patent: September 22, 2015Assignee: Cree, Inc.Inventors: Van Mieczkowski, Helmut Hagleitner, Zoltan Ring
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Publication number: 20150221574Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.Type: ApplicationFiled: February 3, 2014Publication date: August 6, 2015Applicant: Cree, Inc.Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
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Patent number: 8994073Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).Type: GrantFiled: October 4, 2012Date of Patent: March 31, 2015Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Zoltan Ring
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Publication number: 20150084116Abstract: Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width, A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess.Type: ApplicationFiled: September 25, 2013Publication date: March 26, 2015Applicant: CREE, INC.Inventors: Zoltan Ring, Dan Namishia
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Publication number: 20140103363Abstract: A semiconductor die, which includes a substrate, a group of primary conduction sub-layers, and a group of separation sub-layers, is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers.Type: ApplicationFiled: October 17, 2012Publication date: April 17, 2014Applicant: CREE, INC.Inventors: Zoltan Ring, Helmut Hagleitner, Daniel Namishia, Fabian Radulescu
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Publication number: 20140097469Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device and methods of fabrication thereof are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).Type: ApplicationFiled: October 4, 2012Publication date: April 10, 2014Inventors: Helmut Hagleitner, Zoltan Ring
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Patent number: 8563372Abstract: A method of forming a semiconductor device, the method comprising providing a semiconductor layer, and providing a first layer of a first metal on the semiconductor layer. A second layer may be provided on the first layer of the first metal. The second layer may include a layer of silicon and a layer of a second metal, and the first and second metals may be different. The first metal may be titanium and the second metal may be nickel. Related devices, structures, and other methods are also discussed.Type: GrantFiled: February 11, 2010Date of Patent: October 22, 2013Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Zoltan Ring, Scott Sheppard, Jason Henning, Jason Gurganus, Dan Namishia
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Patent number: 8202796Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.Type: GrantFiled: February 7, 2011Date of Patent: June 19, 2012Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Publication number: 20120115319Abstract: The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.Type: ApplicationFiled: November 10, 2010Publication date: May 10, 2012Applicant: CREE, INC.Inventors: Van Mieczkowski, Zoltan Ring, Jason Gurganus, Helmut Hagleitner