Abstract: A satellite communication system which performs multicast switching on data cells. A switch 80 receives the data cells at a set of input ports IP1 and directs those including a multicast routing code to a first set of output ports OP2 or OP128. The switch 80 also directs data cells effectively omitting the multicast routing code to a second set of output ports OP1. One or more multicast replication modules 110, 130 are coupled to the first set of output ports and replicate data cells requiring multicast processing. During the processing, the multicast routing code is effectively omitted and the replicated cells are coupled to input ports IP2 or IP 128 so that the replicated data cells are transmitted to the second set of output ports OP1. An outbound processing module 100 is coupled to output ports OP1 for processing the data cells for transmission over a satellite downlink transmitter 104.

Abstract: A processing satellite proxy cache subsystem for a satellite payload (106) includes an uplink demodulator and decoder (108) for recovering a resource information request from a satellite uplink, a proxy cache (118) comprising a cache memory (210), a processor (204), and a switch (116) coupled to the uplink demodulator and decoder (108) and to the web proxy cache (118). The switch (116) couples to the web proxy cache (118) through a switch output port connection (120) that directs the resource information request to the web proxy cache (118). The processor (204) is responsive to the resource information request for retrieving resource information content associated with the information request from the cache memory (210) for downlinking to the requesting user terminal (102).

Abstract: A caching subsystem and method for a communication satellite includes an uplink demodulator that produces demodulated data on a demodulated data output for storage in a memory cache. This also includes a switched-router coupled to the solid state recorder. A processor outputs a first preselected time delay control signal to the memory cache to generate a first time delayed data stream. In addition, the processor subsequently outputs a second preselected time delay control signal to the solid state recorder to generate a second time delayed data stream. The solid state recorder and processor act in concert to provide a variable time delay pipeline for program data. The uplink demodulator also produces a program data identifier and a delivery request. The processor outputs a control signal to the solid state recorder to generate independent downlink data streams from the program data at delivery times and delivery dates specified by delivery requests.

Abstract: A simplified method for rotating a digital image through a small angle without the need for interpolation is described. The image is divided into small, square blocks, arranged in horizontal rows where each block is exactly to the left or right of the other blocks in the row, and into columns where each block in the column is offset to the right by one pixel with respect to the next higher block. The rotation is then accomplished by moving the lower rows to the left so that the columns are exactly vertical, and by moving the rightmost columns in a downward direction so that each block is one pixel below the block to its left. The result is a rotation of the image through a small angle. There is a considerable simplification gained from not rotating the data within each block which results in a slight distortion of the image, but for small angles, this is not noticeable.