Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.

Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.

Abstract: A contact process for a semiconductor device is described. A substrate having a doped region and a dielectric layer over the doped region is provided. A contact hole is formed through the dielectric layer and exposing the doped region. An insulating liner layer is formed a in the contact hole. A portion of the insulating liner layer at a bottom of the contact hole is etch-removed and over-etching is performed. A conductive epitaxial layer is formed from the doped region in the contact hole, and then the contact hole is filled with a conductive material.

Abstract: A contact process for a semiconductor device is described. A substrate having a doped region and a dielectric layer over the doped region is provided. A contact hole is formed through the dielectric layer and exposing the doped region. An insulating liner layer is formed a in the contact hole. A portion of the insulating liner layer at a bottom of the contact hole is etch-removed and over-etching is performed. A conductive epitaxial layer is formed from the doped region in the contact hole, and then the contact hole is filled with a conductive material.

Abstract: A semiconductor device includes polysilicon layer and a metal silicide layer. The polysilicon layer is doped with carbon or phosphorous. The silicide layer is formed over the polysilicon layer.

Abstract: A semiconductor device includes polysilicon layer and a metal silicide layer. The polysilicon layer is doped with carbon or phosphorous. The silicide layer is formed over the polysilicon layer.