Abstract: A micro-controller including a secure world, a non-secure world, and a processing circuit is provided. The secure world includes a key management device, a decryption circuit, and a first memory. The key management device stores a secret key. The decryption circuit utilizes the secret key to decrypt an encrypted model to generate a decrypted model. The first memory stores the decrypted model. The non-secure world includes a second memory and a third memory. The second memory stores the encrypted model. The third memory stores an inference result. The processing circuit provides input data to the decrypted model. The decrypted model generates the inference result according to the input data.

Abstract: A micro-controller including a non-secure world, a secure world, and a processing circuit is provided. The non-secure world stores a neural network model including an encrypted operator and an un-encrypted operator. The secure world stores a key and includes a decryption circuit. In a non-secure mode, the processing circuit interprets the un-encrypted operator. In a secure mode, the processing circuit directs the decryption circuit to use the key to decrypt the encrypted operator to generate a decrypted result. In the secure mode, the processing circuit interprets the decrypted result to generate second output data and stores the second output data in the non-secure world.

Abstract: An event trigger master coupled to a first peripheral device and including an event receiving interface, a storage element, a state machine, and a master interface is provided. The event receiving interface is configured to receive an event request. The storage element includes a command queue to store a set command. The state machine performs the set command to access the first peripheral device or a second peripheral device in response to the event request being triggered. The master interface is coupled to the state machine, the first peripheral device, and the second peripheral device. The state machine accesses the first or second peripheral device via the master interface.

Abstract: A chip capable of authenticating an off-chip debug firmware program and a debug user account is illustrated. The chip runs the secure boot firmware and executes the secure boot process to verify whether the debug firmware program in a signed program loaded from an external storage device may be executed. After the signed program is successfully verified, the chip runs the debug firmware program to execute a debug user authentication algorithm in the signed program, thereby starting a debug user authentication process. After verifying the debug user account of the external debugging tool connected to the chip is a valid debug user account, the debugging tool is allowed to use the debugging function in the chip according to the authority of the debug user.

Abstract: A method for protecting data in an external memory based on an isolated execution environment is provided. The method is used in a processor in the isolated execution environment of a system-on-a-chip. The method includes: accessing an output command of a main system processor in a main system of the system-on-a-chip; reading first data from a shared memory in the main system according to the output command; encrypting the first data with a private key and generating encrypted first data; and outputting the encrypted first data to the external memory.

Abstract: An electronic device includes a first memory controller, a second memory controller, and a memory access controller. The first memory controller stores setting information of a predetermined memory, wherein the predetermined memory is defined as an execute-only-memory. The second memory controller provides and sets an enabling register according to the setting information of the predetermined memory, and generates an enabling signal. The memory access controller accesses the first memory controller and the second memory controller to move the data of the predetermined memory to a predetermined memory space corresponding to the enabling register according to the enabling signal and the setting information of the predetermined memory.

Abstract: A chip capable of authenticating an off-chip debug firmware program and a debug user account is illustrated. The chip runs the secure boot firmware and executes the secure boot process to verify whether the debug firmware program in a signed program loaded from an external storage device may be executed. After the signed program is successfully verified, the chip runs the debug firmware program to execute a debug user authentication algorithm in the signed program, thereby starting a debug user authentication process. After verifying the debug user account of the external debugging tool connected to the chip is a valid debug user account, the debugging tool is allowed to use the debugging function in the chip according to the authority of the debug user.

Abstract: An event trigger master coupled to a first peripheral device and including an event receiving interface, a storage element, a state machine, and a master interface is provided. The event receiving interface is configured to receive an event request. The storage element includes a command queue to store a set command. The state machine performs the set command to access the first peripheral device or a second peripheral device in response to the event request being triggered. The master interface is coupled to the state machine, the first peripheral device, and the second peripheral device. The state machine accesses the first or second peripheral device via the master interface.

Abstract: A method for protecting data in an external memory based on an isolated execution environment is provided. The method is used in a processor in the isolated execution environment of a system-on-a-chip. The method includes: accessing an output command of a main system processor in a main system of the system-on-a-chip; reading first data from a shared memory in the main system according to the output command; encrypting the first data with a private key and generating encrypted first data; and outputting the encrypted first data to the external memory.

Abstract: A semiconductor device includes a debug port, a first access port, a second access port, a first processing unit, a second processing unit, and an embedded emulator unit. The first access port is coupled to the debug port. The second access port is coupled to the debug port. The first processing unit is coupled to the first access port. The second processing unit is coupled to the second access port. The embedded emulator unit is coupled to the debug port, the first processing unit and the second processing unit. The first processing unit generates a debug instruction to access the embedded emulator unit, so that the embedded emulator unit generates a debug signal. The debug signal is output to the second processing unit through the debug port and the second access port, so as to perform a debug operation on the second processing unit.

Abstract: An electronic device includes a first memory controller, a second memory controller, and a memory access controller. The first memory controller stores setting information of a predetermined memory, wherein the predetermined memory is defined as an execute-only-memory. The second memory controller provides and sets an enabling register according to the setting information of the predetermined memory, and generates an enabling signal. The memory access controller accesses the first memory controller and the second memory controller to move the data of the predetermined memory to a predetermined memory space corresponding to the enabling register according to the enabling signal and the setting information of the predetermined memory.

Abstract: A semiconductor device includes a debug port, a first access port, a second access port, a first processing unit, a second processing unit, and an embedded emulator unit. The first access port is coupled to the debug port. The second access port is coupled to the debug port. The first processing unit is coupled to the first access port. The second processing unit is coupled to the second access port. The embedded emulator unit is coupled to the debug port, the first processing unit and the second processing unit. The first processing unit generates a debug instruction to access the embedded emulator unit, so that the embedded emulator unit generates a debug signal. The debug signal is output to the second processing unit through the debug port and the second access port, so as to perform a debug operation on the second processing unit.

Abstract: A computer apparatus is provided, which includes a plurality of peripheral apparatuses, a non-volatile memory, a processor, and an authority-control circuit. The memory unit stores a plurality of boot codes and setting values of a function set of the peripheral apparatuses corresponding to each boot code, wherein the boot codes form a chain of trust. In response to the execution of a current boot code being completed, the authority-control circuit sets the setting values of the functions in a second function set corresponding to a next boot code in the chain of trust, sends an authority-control signal to control the peripheral apparatuses corresponding to the second function set according to the setting values of the functions in the second function set, and sets a boot flag corresponding to the next boot code in the authority-control circuit to control the processor to execute the next boot code.

Abstract: A computer apparatus is provided, which includes a plurality of peripheral apparatuses, a non-volatile memory, a processor, and an authority-control circuit. The memory unit stores a plurality of boot codes and setting values of a function set of the peripheral apparatuses corresponding to each boot code, wherein the boot codes form a chain of trust. In response to the execution of a current boot code being completed, the authority-control circuit sets the setting values of the functions in a second function set corresponding to a next boot code in the chain of trust, sends an authority-control signal to control the peripheral apparatuses corresponding to the second function set according to the setting values of the functions in the second function set, and sets a boot flag corresponding to the next boot code in the authority-control circuit to control the processor to execute the next boot code.