Patents by Inventor Zong-You Luo
Zong-You Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369407Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
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Publication number: 20230363287Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20230360686Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Patent number: 11778923Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.Type: GrantFiled: November 14, 2021Date of Patent: October 3, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Patent number: 11749328Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: GrantFiled: July 25, 2022Date of Patent: September 5, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Patent number: 11742388Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: GrantFiled: July 22, 2022Date of Patent: August 29, 2023Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
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Patent number: 11605670Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.Type: GrantFiled: May 1, 2019Date of Patent: March 14, 2023Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu
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Publication number: 20230015775Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: ApplicationFiled: July 22, 2022Publication date: January 19, 2023Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
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Publication number: 20220359615Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu
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Publication number: 20220358980Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Patent number: 11411082Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: GrantFiled: October 1, 2019Date of Patent: August 9, 2022Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
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Patent number: 11410714Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.Type: GrantFiled: September 16, 2019Date of Patent: August 9, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Publication number: 20220077384Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.Type: ApplicationFiled: November 14, 2021Publication date: March 10, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Patent number: 11177430Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.Type: GrantFiled: June 17, 2019Date of Patent: November 16, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Publication number: 20210082482Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20200395530Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20200144367Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: ApplicationFiled: October 1, 2019Publication date: May 7, 2020Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, CheeWee Chee-Wee Liu
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Publication number: 20200135804Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.Type: ApplicationFiled: May 1, 2019Publication date: April 30, 2020Inventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu