Abstract: Methods and systems for identifying defects in an integrated circuit are provided. The method includes receiving input data of a pattern associated with an integrated circuit, determining feature data associated with features of the pattern using the input data, determining defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determining a defect identification result using the defect detection results. The system includes a processor and a memory. The memory is coupled to the processor and configured to store a set of instructions to receive input data of a pattern associated with an integrated circuit, determine feature data associated with features of the pattern using the input data, determine defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determine a defect identification result using the defect detection results.

Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.

Abstract: A method, a non-transitory computer-readable medium, and an apparatus for optimizing a design layout of an integrated circuit (IC) includes: selecting layout regions from a full-chip design layout for the IC; determining pixel images for the layout regions by performing pixel-based mask optimization for the layout regions, in which each pixel image corresponds to a respective layout region; determining a backpropagation (BP) artificial neural network (ANN) model using the pixel images and the layout regions; and determining a full-chip pixel image for the full-chip design layout using the BP ANN model, in which the BP ANN model uses the full-chip design layout as input.

Abstract: Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.

Abstract: A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.

Abstract: A method, a non-transitory computer-readable medium, and an apparatus for optimizing a design layout of an integrated circuit (IC) includes: selecting layout regions from a full-chip design layout for the IC; determining pixel images for the layout regions by performing pixel-based mask optimization for the layout regions, in which each pixel image corresponds to a respective layout region; determining a backpropagation (BP) artificial neural network (ANN) model using the pixel images and the layout regions; and determining a full-chip pixel image for the full-chip design layout using the BP ANN model, in which the BP ANN model uses the full-chip design layout as input.

Abstract: Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.

Abstract: A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.

Abstract: Methods and systems for identifying defects in an integrated circuit are provided. The method includes receiving input data of a pattern associated with an integrated circuit, determining feature data associated with features of the pattern using the input data, determining defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determining a defect identification result using the defect detection results. The system includes a processor and a memory. The memory is coupled to the processor and configured to store a set of instructions to receive input data of a pattern associated with an integrated circuit, determine feature data associated with features of the pattern using the input data, determine defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determine a defect identification result using the defect detection results.

Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.