Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a first stop layer on the sacrificial layer, an N-type doped semiconductor layer on the first stop layer, and a dielectric stack on the N-type doped semiconductor layer are sequentially formed. A plurality of channel structures each extending vertically through the dielectric stack and the N-type doped semiconductor layer are formed, stopping at the first stop layer. The dielectric stack is replaced with a memory stack, such that each of the plurality of channel structures extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose an end of each of the plurality of channel structures. A conductive layer is formed in contact with the ends of the plurality of channel structures.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

Abstract: A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. The first stack includes a first array region and a first staircase region adjacent to the first array region. The semiconductor device includes a second stack of alternating second word line layers and second insulating layers, where the second stack includes a second array region over the first array region and a second staircase region adjacent to the second array region and over the first staircase region. The first stack further includes a first transition layer over the first word line layers. The first transition layer includes a first dielectric portion in the first array region that surrounds the first channel structure and a first conductive portion. The first transition layer is disposed between two adjacent first insulating layers of the first insulating layers.

Abstract: A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.

Abstract: The present invention discloses an experimental device for cavitation corrosion of liquid metal, comprising a stand, and a vibration device and a lifting and rotating device separately arranged on the stand, wherein a heating device for experimental use is arranged on the vibration device; a furnace lid with a sealing ring is arranged above the heating device; a stirring mechanism is arranged on the furnace lid; the stirring mechanism is connected to a chunk below the furnace lid; a clamp is connected below the chuck, and the clamp is connected to a sample; the furnace lid is connected to the lifting and rotating device; the lifting and rotating device can control the movement of the furnace lid so that the sample is placed in the heating device; the lifting and rotating device, the stirring mechanism, the heating device and the vibration device are connected to a control system.

Abstract: The present invention discloses an experimental device for cavitation corrosion of liquid metal, comprising a stand, and a vibration device and a lifting and rotating device separately arranged on the stand, wherein a heating device for experimental use is arranged on the vibration device; a furnace lid with a sealing ring is arranged above the heating device; a stirring mechanism is arranged on the furnace lid; the stirring mechanism is connected to a chunk below the furnace lid; a clamp is connected below the chuck, and the clamp is connected to a sample; the furnace lid is connected to the lifting and rotating device; the lifting and rotating device can control the movement of the furnace lid so that the sample is placed in the heating device; the lifting and rotating device, the stirring mechanism, the heating device and the vibration device are connected to a control system.

Abstract: A hydraulic ship lift, including: a mechanical synchronizing system; a stabilizing and equalizing hydraulic driving system; and a self-feedback stabilizing system. The stabilizing and equalizing hydraulic driving system includes first resistance equalizing members arranged at corners of branch water pipes or/and second resistance equalizing members arranged at bifurcated pipes, circular forced ventilating mechanisms arranged at front of water delivery valves of a water delivery main pipe, and pressure-stabilizing and vibration-reducing boxes arranged behind the water delivery valves. The self-feedback stabilizing system includes a plurality of guide wheels; each guide wheel of the self-feedback stabilizing system is fixed on a ship reception chamber through a supporting mechanism.

Abstract: A hydraulic ship lift, including: a mechanical synchronizing system; a stabilizing and equalizing hydraulic driving system; and a self-feedback stabilizing system. The stabilizing and equalizing hydraulic driving system includes first resistance equalizing members arranged at corners of branch water pipes or/and second resistance equalizing members arranged at bifurcated pipes, circular forced ventilating mechanisms arranged at front of water delivery valves of a water delivery main pipe, and pressure-stabilizing and vibration-reducing boxes arranged behind the water delivery valves. The self-feedback stabilizing system includes a plurality of guide wheels; each guide wheel of the self-feedback stabilizing system is fixed on a ship reception chamber through a supporting mechanism.