Patents by Inventor Zongming JIA

Zongming JIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11816038
    Abstract: A method and an apparatus of mapping table reconstruction based on a SSD, and a computer device are disclosed by the present application, and the method includes: acquiring the mapping table reconstruction request based on the SSD; scanning starting from the last physical page of the corresponding physical block according to the mapping table reconstruction request based on the SSD; reading the corresponding logical address and N logical address offsets from a data area of the current physical page, where N is the positive integer greater than 1; acquiring logical addresses corresponding to N adjacent pages in sequence according to the logical address corresponding to the current physical page and the N logical address offsets; reconstructing a mapping relationship between logical addresses and physical addresses according to the logical address corresponding to the current physical page and the logical addresses corresponding to the N adjacent pages.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 14, 2023
    Assignee: SHENZHEN UNIONMEMORY INFORMATION SYSTEM LIMITED
    Inventors: Xuesen Yang, Jian Li, Longhua Qin, Jintao Gan, Weiliang Wang, Zongming Jia
  • Publication number: 20230131779
    Abstract: A method and an apparatus of mapping table reconstruction based on a SSD, and a computer device are disclosed by the present application, and the method includes: acquiring the mapping table reconstruction request based on the SSD; scanning starting from the last physical page of the corresponding physical block according to the mapping table reconstruction request based on the SSD; reading the corresponding logical address and N logical address offsets from a data area of the current physical page, where N is the positive integer greater than 1; acquiring logical addresses corresponding to N adjacent pages in sequence according to the logical address corresponding to the current physical page and the N logical address offsets; reconstructing a mapping relationship between logical addresses and physical addresses according to the logical address corresponding to the current physical page and the logical addresses corresponding to the N adjacent pages.
    Type: Application
    Filed: February 28, 2020
    Publication date: April 27, 2023
    Inventors: Xuesen YANG, Jian LI, Longhua QIN, Jintao GAN, Weiliang WANG, Zongming JIA
  • Publication number: 20230120680
    Abstract: The present application discloses a method and a device for marking dirty bits of an L2P table based on a SSD, the method includes: obtaining a marking request of dirty bits in the L2P table based on the solid state drive; and broadening a corresponding dirty bit in the L2P table to 2 bits according to the request; and setting the dirty bit from a binary number 00 to a binary number 01 through a state machine when a first write command request is obtained; setting the dirty bit from the binary number 01 to a binary number 10 through the state machine when flush operation starts; and setting the dirty bit from the binary number 10 to a binary number 11 through the state machine when a second write command request is obtained during the flush operation.
    Type: Application
    Filed: February 26, 2020
    Publication date: April 20, 2023
    Inventors: An YU, Haidong ZHENG, Haibin WANG, Jintao GAN, Weiliang WANG, Zongming JIA
  • Patent number: 11429533
    Abstract: A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 30, 2022
    Assignee: SHENZHEN UNIONMEMORY INFORMATION SYSTEM LIMITED
    Inventors: Jian Zuo, Yuanyuan Feng, Zhiyuan Leng, Jintao Gan, Weiliang Wang, Zongming Jia
  • Publication number: 20210019265
    Abstract: A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 21, 2021
    Inventors: Jian ZUO, Yuanyuan FENG, Zhiyuan LENG, Jintao GAN, Weiliang WANG, Zongming JIA