Abstract: A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

Abstract: A device may include memory media; storage media; a buffer; and at least one circuit configured to perform one or more operations including receiving memory address information; storing the memory address information in the buffer; determining that data may be loaded to the memory media; and loading data to the memory media, from the storage media, corresponding to the memory address information in the buffer. In some aspects, the memory address information is first memory address information; the data is first data; and the at least one circuit is further configured to perform one or more operations including receiving a memory access request including second memory address information; determining to load second data based on the memory access request; and loading the second data to the memory media, from the storage media, based on the second memory address information.

Abstract: A cache-coherent persistent memory (PMEM) device includes an input/output (I/O) interface; a volatile memory module; an error correction module which is configurable according to an I/O protocol; a non-volatile storage module; and at least one processor configured to: receive a store command and data corresponding to the store command from a host device through the I/O interface, based on the store command, control the volatile memory module to store the data, control the error correction module to encode the data to generate encoded data, and control the non-volatile storage module to store the encoded data.

Abstract: The present disclosure discloses a child safety seat, which is for being installed on a vehicle seat. The child safety seat includes a base having an anchor part connected to the vehicle seat; a seat coupled to the base; a top rod fixed to the rear of the base; a tether assembly including a top tether and a tether fixing portion that are connected with each other, the top tether being connected with the top rod and the tether fixing portion being connected with the vehicle seat; and an alarm device including a switch which can be triggered when the top tether is tightened. The present disclosure also discloses a tether assembly and a support structure. The child safety seat can conveniently prompt that it is not correctly fixed, and can be conveniently fixed and adjusted, thereby improving the safety and riding comfort of the child safety seat.

Abstract: A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the reading storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.

Abstract: A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.

Abstract: Provided is a method for data storage, the method including receiving a first request at a storage device, the first request being associated with a first protocol that is a memory protocol, converting address information associated with the first request to logical block address (LBA) information, determining, by the storage device, a first group of contiguous physical block addresses associated with the first request and associated with a first application, based on a data placement configuration of the storage device, and performing a first memory operation at the first group, based on the first request.

Abstract: A device may include a first memory media, a second memory media, and at least one control circuit configured to receive placement information for data, store, in a portion of the first memory media, based on the placement information, the data, and store, in a portion of the second memory media, based on the placement information, the data. The at least one control circuit may be configured to receive a request to access, from the portion of the first memory media, the data, and access, based on the request, from the portion of the second memory media, the data. The at least one control circuit may be configured to modify, based on an allocation status, the portion of the first memory media to an available state.

Abstract: A device may include a storage medium, a cache medium, a buffer medium, and at least one control circuit configured to perform one or more operations including receiving a first request to access the storage medium, accessing, based on the first request, the cache medium, copying, from a portion of the storage medium to the buffer medium, data, modifying, based on the copying, an availability of the at least a portion of the storage medium, receiving a second request to access the storage medium, and accessing, based on the second request, the buffer medium. The one or more operations may include determining a location of data associated with the second request, and accessing, based on the determining, the buffer medium. The one or more operations may include receiving information about a location of data associated with the second request, and accessing, based on the information, the buffer medium.

Abstract: Systems and methods for prefetching data are disclosed. A processor in communication with a storage device identifies a first address. The processor identifies a first setting associated with the first address. The processor issues a first command to a first storage medium of the storage device based on the first setting. The first command is for performing a first type of memory read. The storage device is configured to retrieve first data associated with the first address in the first storage medium, to a second storage medium of the storage device, based on the first command.

Abstract: Systems and methods for cache management of a storage device are disclosed. The storage device is configured to receive a first code provided by a computing device; execute the first code; perform a first update of the first storage medium based on the first code; receive a second code provided by the computing device; execute the second code; and perform a second update of the first storage medium based on the second code.

Abstract: Systems and methods for prefetching data are disclosed. A processor executes a first command for moving first data stored in a storage device. Based on the first command, the processor stores, into a first queue of the storage device, a first address associated with the first data. The storage device further retrieves the first address from the first queue, retrieves the first data from the first storage medium based on the first address, and stores the first data to the second storage medium. In some embodiments, a process for prefetch optimization is also disclosed. A processor identifies a value for prefetching data. The processor runs an application, measures performance of the application, modifies the value based on the performance, and determines that the performance satisfies a criterion.

Abstract: A device may include cache media, storage media, a communication interface configured to communicate with the cache media and the storage media, and at least one control circuit to configure a portion of the storage media as visible memory, and configure a portion of the cache media as a cache for the portion of the storage media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media to persist the portion of the cache media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media as visible storage.

Abstract: A system is disclosed. A processor may include a local memory. A memory may be connected to the processor. A cache-coherent interconnect storage device may also be connected to the processor. An embedded management unit (EMU) may be configured to manage the storage of a document embedding vector in the local memory, the memory, or the cache-coherent interconnect storage device.

Abstract: A system is disclosed. A storage device may store a document embedding vector. An accelerator connected to the storage device may be configured to process a query embedding vector and the document embedding vector. A processor connected to the storage device and the accelerator may be configured to transmit the query embedding vector to the accelerator.

Abstract: Provided is a method of data storage, the method including receiving, from an application, a request to access data stored on a storage device, identifying a data access pattern of the application, and storing the data in a cache of the storage device based on the data access pattern.

Abstract: Systems and methods for a storage system are disclosed. The storage system includes a first storage medium, a processor configured to communicate with the first storage medium, and a memory coupled to the processor. The memory stores instructions that, when executed by the processor, cause the processor to: receive a request for accessing data; search the first storage medium based on the request; receive a command from a computing device, the command including a configuration parameter; and based on the command, modify architecture of the first storage medium from a first architecture to a second architecture corresponding to the configuration parameter.

Abstract: A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.

Abstract: A method for reordering data for storage includes detecting a data access pattern, associated with an application, for accessing a data, generating a remapping function based on a data access pattern information, the remapping function including operations to determine a reordering of the data based on address information for the data, receiving the data at a storage device, the data being ordered according to a first layout sequence, reordering the data, by the storage device, based on the remapping function, and storing the data, at the storage device, according to a second layout sequence corresponding to the data access pattern, the second layout sequence being different than the first layout sequence.

Abstract: A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.