Abstract: A full-analog vector matrix multiplication process-in-memory circuit comprises: an input circuit, a device array, an output clamping circuit, and an analog shift-and-add unit. The input circuit is used for sampling and holding analog input data and inputting the sampled analog input data into an array. The device array consists of resistive devices and is used for storing a weight value in the form of conductance and performing vector matrix multiplication calculation on the analog input data and the weight value. The output clamping circuit is used for clamping an output point of the device array to a zero level and converting a calculation result in the form of current into a result in the form of voltage for output. The analog shift-and-add unit is used for shifting and adding calculation results of devices in columns of the device array to complete carry calculation.

Abstract: The present disclosure provides a storage array including memory cells arranged in a matrix array, each memory cell includes two memories, one P-channel field effect transistor and two N-channel field effect transistors alternately connected to the P-channel field effect transistor; a source of the P-channel field effect transistor is connected to a drain of a N-channel field effect transistor, a drain of the P-channel field effect transistor is connected to a source of the N-channel field effect transistor, and the two memories are respectively connected to the source of the P-channel field effect transistor and the source of the N-channel field effect transistor. The present disclosure can improve the density of the storage array and reduce the requirement for the drive capability of the field effect transistor.

Abstract: The embodiments of the present application relate to the technical field of integrated circuit packaging. Provided are a packaging structure and an integrated circuit board. The packaging structure includes: a substrate having a plurality of first conductive layers and a plurality of second conductive layers, where the first conductive layers and the second conductive layers have different electric property types; a redistribution structure including redistribution layers at a plurality of layers and arranged at intervals, wherein the redistribution layers located at the same layer have the same electric property type, and the redistribution layers located at adjacent layers have different electric property types; and a plurality of conductive bumps electrically connected to the first conductive layers or the second conductive layers through the redistribution structure.

Abstract: A scenario setting method and an electronic device are provided, and relate to the field of terminal technologies. In an electronic device control process, a real-time scenario is automatically generated in response to a user operation, thereby reducing a scenario setting difficulty and improving user experience. The method includes: A control device displays a first interface including a trigger area, displays, in the trigger area, a first identifier of a first device that executes a first intention, and displays, outside the trigger area, a second identifier of a second device that does not execute a second intention. The control device generates, in response to a user operation, a scenario corresponding to the first interface, where the scenario includes indicating the first device to execute the first intention, and indicating the second device to cancel execution of the second intention.

Abstract: A compute-in-memory circuit based on charge redistribution includes a memory array, multiple-functional output units (MFUs), multiplexers (MUXs), and a word line (WL) driver. The memory array includes memory cell rows and memory cell columns. Every two adjacent memory cells form a memory cell pair in sequence, and every two adjacent memory cell columns form a memory cell column pair in sequence. A grounded register capacitor is connected to a source line (SL) of each memory cell row. Input ends of each MFU are connected to a first bit line (BL) and a second BL of each memory cell column pair, respectively. Each MUX includes voltage-input ends and an output end, and the output end of each MUX is connected to the SL of each memory cell row in a one-to-one correspondence. An output end of the WL driver is connected to a WL of each memory cell row.

Abstract: A compute-in-memory (CIM) circuit and a control method thereof. The CIM circuit includes a memory array. The memory array comprises n1 memory blocks arranged in sequence from top to bottom, and each memory block comprises n2 rows of memory-cell rows arranged in sequence, wherein n1?2, n2?1. Each odd memory block and an adjacent even memory block arranged therebelow form a memory group. Each memory group comprises n2 pairs of memory-cell rows, and a k-th pair of memory-cell rows in each memory group includes a k-th memory-cell row and a (2n2+1?k)-th memory-cell row in the corresponding memory group, where 1?k?n2. The memory array is divided into n2 memory subarrays configured to be turned on in sequence for calculation, wherein a k-th memory subarray includes the k-th pair of memory-cell rows in each memory group.

Abstract: A memristor-based in-memory logic circuit and in-memory logic computation system, and applications, pertaining to the technical field of integrated circuits, are provided. The in-memory logic circuit includes: a first memory cell and a second memory cell connected in parallel to each other, and a sense amplifier for generating a logic operation result. The two memory cells include memristors and MOSFET selectors connected in series. Resistance states of the two memristors are used to represent a first group of logic input signals, and voltage signals applied by gates of the two MOSFET selectors are used to represent a second group of logic input signals. Also provided are an in-memory logic computation system and applications.

Abstract: A message reply method includes displaying a first user interface including a message list, receiving a first trigger operation performed by a user on a first message box in the message list, where the first trigger operation is for triggering replying to a first contact corresponding to the first message box, obtaining, based on the first trigger operation, a reply message to the first contact when the first user interface is displayed, and sending the reply message to the first contact such that a user may implement a reply to a contact in a message list without opening a specific chat page.

Abstract: A device control method, includes a first electronic device that detects a preset operation of a user in a chat interface of an instant messaging application. The first electronic device displays a list in the chat interface in response to the preset operation, where the list includes device information of one or more devices, the one or more devices are associated with a first account, and the first account is a logged-in account on the instant messaging application. When detecting that the user selects the second electronic device from the list and enters a first instruction for the second electronic device, the first electronic device sends the first instruction to the second electronic device. The second electronic device executes the first instruction.

Abstract: Disclosed in Disclosed are a resistive random access memory and a manufacturing method. A memory area of the resistive random access memory comprises a first metal interconnection line, a resistive random access memory unit and a second metal interconnection line that are connected in sequence, wherein the whole or part of a bottom electrode of the resistive random access memory unit is arranged in a short through hole of a barrier layer on the first metal interconnection line; the first metal interconnection line is connected to the bottom electrode of the resistive random access memory unit; and the second metal interconnection line is connected to a top electrode of the resistive random access memory unit.

Abstract: The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al2O3 is performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of Al2O3, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.

Abstract: Disclosed are a multi-value nonvolatile organic resistive random access memory and a method for preparing the same. The resistive random access memory comprises a top electrode, a bottom electrode and a middle functional layer located between the top electrode and the bottom electrode, the middle functional layer is at least two layers of parylene. The method comprises the steps of: growing material for the bottom electrode using physical vapor deposition method on a substrate; growing sequentially multiple layers of parylene on the bottom electrode by polymer chemical vapor deposition; defining the via for leading out the bottom electrode by lithography and etching; growing material for the top electrode on the parylene materials by using physical vapor deposition process, defining the top electrode material by lithography and lift-off, and leading out the bottom electrode.

Abstract: The present invention discloses a time correlation learning neuron circuit based on a resistive memristor and an implementation method thereof. The present invention utilizes switching characteristics of the resistive memristor. When two terminals of the resistive memristor are selected synchronously by two excitation signals, the voltage drop between these two terminals will change the resistance value of memristor, thereby achieving the on-off of a synapse connection and achieving the correction of the two excitation signals. Meanwhile the device also has a memory characteristic. Also, the previous excitation signal can be repeated. That is, the purpose of learning is achieved. Since the resistive memristor has a simple structure and a high degree of integration, it can achieve large-scale physical synapse connection in order to achieve more complex learning and even logic functions. The present invention has a good application prospect in a neuron cell computation.

Abstract: The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al2O3 is performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of Al2O3, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.

Abstract: The present invention provides a method for establishing an inter-domain path that satisfies wavelength continuity constraint. The fPCE stores a virtual topology comprised by border nodes of all domains. The present invention uses parallel inter-domain path establishment method to decrease the influence from WCC. Compared with the sequential process way in prior art, it enhanced the resource utilization and decreased computation delay.

Abstract: The present invention provides a method for establishing an inter-domain path that satisfies wavelength continuity constraint. The fPCE stores a virtual topology comprised by border nodes of all domains. The present invention uses parallel inter-domain path establishment method to decrease the influence from WCC. Compared with the sequential process way in prior art, it enhanced the resource utilization and decreased computation delay.