Abstract: A message reply method includes displaying a first user interface including a message list, receiving a first trigger operation performed by a user on a first message box in the message list, where the first trigger operation is for triggering replying to a first contact corresponding to the first message box, obtaining, based on the first trigger operation, a reply message to the first contact when the first user interface is displayed, and sending the reply message to the first contact such that a user may implement a reply to a contact in a message list without opening a specific chat page.

Abstract: A device control method, includes a first electronic device that detects a preset operation of a user in a chat interface of an instant messaging application. The first electronic device displays a list in the chat interface in response to the preset operation, where the list includes device information of one or more devices, the one or more devices are associated with a first account, and the first account is a logged-in account on the instant messaging application. When detecting that the user selects the second electronic device from the list and enters a first instruction for the second electronic device, the first electronic device sends the first instruction to the second electronic device. The second electronic device executes the first instruction.

Abstract: Disclosed in Disclosed are a resistive random access memory and a manufacturing method. A memory area of the resistive random access memory comprises a first metal interconnection line, a resistive random access memory unit and a second metal interconnection line that are connected in sequence, wherein the whole or part of a bottom electrode of the resistive random access memory unit is arranged in a short through hole of a barrier layer on the first metal interconnection line; the first metal interconnection line is connected to the bottom electrode of the resistive random access memory unit; and the second metal interconnection line is connected to a top electrode of the resistive random access memory unit.

Abstract: The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al2O3 is performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of Al2O3, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.

Abstract: Disclosed are a multi-value nonvolatile organic resistive random access memory and a method for preparing the same. The resistive random access memory comprises a top electrode, a bottom electrode and a middle functional layer located between the top electrode and the bottom electrode, the middle functional layer is at least two layers of parylene. The method comprises the steps of: growing material for the bottom electrode using physical vapor deposition method on a substrate; growing sequentially multiple layers of parylene on the bottom electrode by polymer chemical vapor deposition; defining the via for leading out the bottom electrode by lithography and etching; growing material for the top electrode on the parylene materials by using physical vapor deposition process, defining the top electrode material by lithography and lift-off, and leading out the bottom electrode.

Abstract: The present invention discloses a time correlation learning neuron circuit based on a resistive memristor and an implementation method thereof. The present invention utilizes switching characteristics of the resistive memristor. When two terminals of the resistive memristor are selected synchronously by two excitation signals, the voltage drop between these two terminals will change the resistance value of memristor, thereby achieving the on-off of a synapse connection and achieving the correction of the two excitation signals. Meanwhile the device also has a memory characteristic. Also, the previous excitation signal can be repeated. That is, the purpose of learning is achieved. Since the resistive memristor has a simple structure and a high degree of integration, it can achieve large-scale physical synapse connection in order to achieve more complex learning and even logic functions. The present invention has a good application prospect in a neuron cell computation.

Abstract: The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al2O3 is performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of Al2O3, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.

Abstract: The present invention provides a method for establishing an inter-domain path that satisfies wavelength continuity constraint. The fPCE stores a virtual topology comprised by border nodes of all domains. The present invention uses parallel inter-domain path establishment method to decrease the influence from WCC. Compared with the sequential process way in prior art, it enhanced the resource utilization and decreased computation delay.

Abstract: The present invention provides a method for establishing an inter-domain path that satisfies wavelength continuity constraint. The fPCE stores a virtual topology comprised by border nodes of all domains. The present invention uses parallel inter-domain path establishment method to decrease the influence from WCC. Compared with the sequential process way in prior art, it enhanced the resource utilization and decreased computation delay.