Patents by Inventor Zongwei Zhu

Zongwei Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240061990
    Abstract: A document generation method includes receiving a first input performed by a user for selecting a type of a to-be-generated document on a photographing preview interface; entering a creation mode for a document of a target type and displaying at least one component of a to-be-generated target document in the creation mode, in response to the first input; receiving a second input performed by a user for adding a picture to the at least one component; capturing a target picture and adding the target picture to the at least one component, in response to the second input; and generating a target document in response to a third input for generating the target document.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Inventors: Zongwei Zhu, Yongchang Guo
  • Publication number: 20210141697
    Abstract: Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes multiple types of HEs (hardware elements) comprising one or more HEs configured to perform operations associated with multi-layer NN (neural network) processing, at least one spare HE, a data buffer to store correctly computed data in a previous layer of multi-layer NN processing computed, and fault tolerance (FT) control logic. The FT control logic is configured to: determine a fault in a current layer NN processing associated with the HE; cause the correctly computed data in the previous layer of multi-layer NN processing to be copied or moved to said at least one spare HE; and cause said at least one spare HE to perform the current layer NN processing using said at least one spare HE and the correctly computed data in the previous layer of multi-layer NN processing.
    Type: Application
    Filed: February 25, 2019
    Publication date: May 13, 2021
    Inventors: Chung Kuang CHIN, Yujie HU, Tong WU, Clifford GOLD, Yick Kei WONG, Xiaosong WANG, Steven SERTILLANGE, Zongwei ZHU
  • Patent number: 10747631
    Abstract: Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes an instruction buffer, processing circuitry, a data buffer, command circuitry, and communication circuitry. During operation, the instruction buffer stores a first hardware instruction and a second hardware instruction. The processing circuitry executes the first hardware instruction, which computes an intermediate stage of an AI model. The data buffer stores data generated from executing the first hardware instruction. The command circuitry determines that the second hardware instruction is a hardware-initiated store instruction for transferring the data from the data buffer. Based on the hardware-initiated store instruction, the communication circuitry transfers the data from the data buffer to a memory device of a computing system, which includes the mission-critical processor, via a communication interface.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 18, 2020
    Assignee: DINOPLUSAI HOLDINGS LIMITED
    Inventors: Yujie Hu, Tong Wu, Xiaosong Wang, Zongwei Zhu, Chung Kuang Chin, Clifford Gold, Steven Sertillange, Yick Kei Wong
  • Publication number: 20190227887
    Abstract: Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes an instruction buffer, processing circuitry, a data buffer, command circuitry, and communication circuitry. During operation, the instruction buffer stores a first hardware instruction and a second hardware instruction. The processing circuitry executes the first hardware instruction, which computes an intermediate stage of an AI model. The data buffer stores data generated from executing the first hardware instruction. The command circuitry determines that the second hardware instruction is a hardware-initiated store instruction for transferring the data from the data buffer. Based on the hardware-initiated store instruction, the communication circuitry transfers the data from the data buffer to a memory device of a computing system, which includes the mission-critical processor, via a communication interface.
    Type: Application
    Filed: June 5, 2018
    Publication date: July 25, 2019
    Applicant: DinoplusAI Holdings Limited
    Inventors: Yujie Hu, Tong Wu, Xiaosong Wang, Zongwei Zhu, Chung Kuang Chin, Clifford Gold, Steven Sertillange, Yick Kei Wong