Patents by Inventor Zongyou Shao

Zongyou Shao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and device for debugging a MIPS-structure CPU with southbridge and northbridge chipsets
    Patent number: 9846625
    Abstract: The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: December 19, 2017
    Assignee: DAWNING INFORMATION INDUSTRY CO., LTD.
    Inventors: Zongyou Shao, Xinchun Liu, Xiaojun Yang, Chenming Zheng, Ying Wang, Hui Wang, Shengjie Liu, Zhibin Hao, Faqing Liang, Wenhao Yao
  • METHOD AND DEVICE FOR DEBUGGING A MIPS-STRUCTURE CPU WITH SOUTHBRIDGE AND NORTHBRIDGE CHIPSETS
    Publication number: 20140157051
    Abstract: The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.
    Type: Application
    Filed: May 20, 2011
    Publication date: June 5, 2014
    Inventors: Zongyou Shao, Xinchun Liu, Xiaojun Yang, Chenming Zheng, Ying Wang, Hui Wang, Zhibin Hao, Faqing Liang, Wenhao Yao