Abstract: A hardware accelerator is disclosed for performing a computational operation in a cryptographic application comprises one or more addressable computational blocks and a plurality of addressable register blocks. A bus is used for data exchange between the blocks in the form of read-from-bus operations and write-to-bus operations in the course of performing the computational operation. A controller for controlling the data exchange performs a block addressing operation using a respective pre-assigned first address of the blocks for addressing the one or more of the blocks involved in a write-to-bus operation in the data exchange. The controller performs a dummy-addressing selection operation to select one or more of the blocks for a dummy addressing operation and a dummy-addressing operation of the selected one or more of the blocks for dummy-addressing the one or more of the selected blocks in the write-to-bus operation.

Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

Abstract: A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or a second potential supply line (106) are each connected directly and individually to all the circuit components via respective individual conductor path structures (V1, V2).

Abstract: A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or a second potential supply line (106) are each connected directly and individually to all the circuit components via respective individual conductor path structures (V1, V2).

Abstract: Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.

Abstract: Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.