Patents by Inventor Zsolt Kovács-Vajna

Zsolt Kovács-Vajna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8873291
    Abstract: An embodiment of a nonvolatile-memory device includes: a body accommodating at least a first semiconductor well and a second semiconductor well; an insulating structure; and at least one nonvolatile memory cell. The cell includes: at least one first control region in the first well; conduction regions in the second well; and a floating gate region, which extends over portions of the first well and of the second well, is capacitively coupled to the first control region and forms a floating-gate memory transistor with the conduction regions. The insulating structure includes: first insulating regions, which separate the floating gate region from the first control region and from the second well outside the conduction regions and have a first thickness; and second insulating regions, which separate the floating gate region from the first well outside the first control region and have a second thickness greater than the first thickness.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 28, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabrizio Torricelli, Luigi Colalongo, Anna Richelli, Zsolt Kovàcs-Vajna
  • Publication number: 20130343128
    Abstract: An embodiment of a nonvolatile-memory device includes: a body accommodating at least a first semiconductor well and a second semiconductor well; an insulating structure; and at least one nonvolatile memory cell. The cell includes: at least one first control region in the first well; conduction regions in the second well; and a floating gate region, which extends over portions of the first well and of the second well, is capacitively coupled to the first control region and forms a floating-gate memory transistor with the conduction regions. The insulating structure includes: first insulating regions, which separate the floating gate region from the first control region and from the second well outside the conduction regions and have a first thickness; and second insulating regions, which separate the floating gate region from the first well outside the first control region and have a second thickness greater than the first thickness.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 26, 2013
    Inventors: Fabrizio TORRICELLI, Luigi COLALONGO, Anna RICHELLI, Zsolt KOVÀCS-VAJNA
  • Publication number: 20060109048
    Abstract: A two-phase charge pump is provided that is capable of being controlled by first and second clock signals that are out-of-phase and take alternatively a first value and a second value during consecutive phases. The charge pump includes a sequence of cascade-connected stages that each have a first section and a second section. Each section includes an input terminal and an output terminal, a capacitive element, and a controlled switch coupling the input terminal of the section with the output terminal of the section. The input terminals in each stage other than the first stage are cross-coupled with the output terminals in a preceding stage. The capacitive element has first and second terminals. The first terminals in the first and second sections receive the first and second clock signals, respectively, and the second terminal is coupled with the output terminal of the section. The controlled switch has a control terminal. In each stage, the control terminals are coupled to each other.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 25, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Luca Mensi, Anna Richelli, Luigi Colalongo, Zsolt Kovacs-Vajna
  • Patent number: 6480617
    Abstract: A method of identifying fingerprints, the method including the steps of acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: November 12, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventor: Zsolt Kovács-Vajna
  • Publication number: 20010040989
    Abstract: A method of identifying fingerprints, the method including the steps of: acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.
    Type: Application
    Filed: April 4, 2001
    Publication date: November 15, 2001
    Inventor: Zsolt Kovacs-Vajna
  • Patent number: 6236741
    Abstract: A method of identifying fingerprints, the method including the steps of: acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: May 22, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Zsolt Kovács-Vajna