Patents by Inventor Zudian Qin

Zudian Qin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated resistance and capacitance extraction and netlist generation of logic cells
    Patent number: 10482212
    Abstract: Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 19, 2019
    Assignee: Synopsys, Inc.
    Inventors: Zudian Qin, Karim El Sayed, Victor Moroz, Xi-Wei Lin
  • Automated Resistance and Capacitance Extraction and Netlist Generation of Logic Cells
    Publication number: 20180239857
    Abstract: Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 23, 2018
    Applicant: Synopsys, Inc.
    Inventors: Zudian Qin, Karim El Sayed, Victor Moroz, Xi-Wei Lin