Abstract: Integrated circuits and methods fabricating memory cells and integrated circuits are provided. In one embodiment, a method for fabricating a memory cell includes doping a semiconductor substrate to define a conductive region. The method includes forming a stacked structure over the semiconductor substrate. The stacked structure lies over the conductive region and includes a control gate overlying a floating gate. A source line region is formed adjacent a first side of the stacked structure. The method includes forming a contact over the semiconductor substrate and adjacent a second side of the stacked structure to define an electrical current path from the source line region through the conductive region under the stacked structure to the contact.

Abstract: A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells and a method of manufacturing the cells are also disclosed.

Abstract: Methods for fabricating memory cells, methods for fabricating integrated circuits having memory cells, and integrated circuits having memory cells are provided. In one example, a method for fabricating a memory cell includes depositing a first tunnel dielectric layer over a semiconductor substrate. The method includes depositing a floating gate material over the first tunnel dielectric layer. The method forms two control gate stacks over the floating gate material, defines a source line area between the two control gate stacks, and defines select gate areas adjacent the two control gate stacks. The method includes depositing a second tunnel dielectric layer over the select gate areas of the semiconductor substrate. Further, the method includes forming select gates over the second tunnel dielectric layer over the select gate areas of the semiconductor substrate. The second tunnel dielectric layer forms a gate dielectric layer for each select gate.

Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.

Abstract: A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall.

Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.

Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.

Abstract: A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall.

Abstract: A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells and a method of manufacturing the cells are also disclosed.

Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.